Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683718
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives A. Document Revision History for Stratix® 10 Low Latency 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the Stratix® 10 LL 40GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Stratix® 10 LL 40GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. Stratix® 10 LL 40GbE Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
A. Document Revision History for Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.3

The Stratix® 10 Low Latency (LL) 40G Ethernet IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the Quartus® Prime IP parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

In addition, you can download the compiled hardware design to the Intel device-specific development kit for interoperative testing. The also includes a compilation-only example project that you can use to quickly estimate IP core area and timing.

The Stratix® 10 Low Latency (LL) 40G Ethernet IP supports design example generation with a wide range of parameters. However, the design examples do not cover all possible parameterizations of the Stratix® 10 LL 40GbE IP Core.

Figure 1. Development Steps for the Design Example

Section Content
Directory Structure
Simulation Design Example Components
Hardware Design Example Components
Generating the Design Example
Simulating the Stratix 10 LL 40GbE Design Example Testbench
Compiling and Configuring the Design Example in Hardware
Testing the Stratix 10 LL 40GbE Hardware Design Example

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