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Ixiasoft
1.3.1. Top Level HDL
The Platform Designer top system, transport layer, test pattern generator and checker, deterministic latency measurement and frequency checker modules are instantiated in the top-level HDL file called jesd204b_ed.sv. The top-level HDL file located at the <project directory>/ directory includes the project parameters that define the configuration of the reference design.
| Parameter | Description |
|---|---|
| LINK | Number of JESD204B link. One link represents one JESD204B instance. A link composed of multiple lanes. Set to match the configuration in JESD204B IP core parameter editor. |
| SUBSYSTEM | Number of JESD204B subsystem in Platform Designer top level system. A JESD204B subsystem may contain multiple links that requires for multi-devices synchronization. |
| L | Number of JESD204B lanes per converter device. Set to match the configuration in JESD204B IP core parameter editor. |
| M | Number of JESD204B converters per device. Set to match the configuration in JESD204B IP core parameter editor. |
| F | Number of JESD204B octets per frame. Set to match the configuration in JESD204B IP core parameter editor. |
| N | Number of JESD204B conversion bits per converter device. Set to match the configuration in JESD204B IP core parameter editor. |
| N_PRIME | Number of JESD204B transmitted bits per sample. Set to match the configuration in JESD204B IP core parameter editor. |
| S | Number of JESD204B transmitted samples per converter device per frame. Set to match the configuration in JESD204B IP core parameter editor. |
| CS | Number of JESD204B control bits per conversion sample. Set to match the configuration in JESD204B IP core parameter editor. |
| F1_FRAMECLK_DIV | Divider ratio for frame_clk when F=1. Refer to the JESD204B IP Core Design Example User Guide for more details. |
| F2_FRAMECLK_DIV | Divider ratio for frame_clk when F=2. Refer to the JESD204B IP Core Design Example User Guide for more details. |
| POLYNOMIAL_LENGTH | Defines the polynomial length for the PRBS pattern generator and checker. Refer to the JESD204B IP Core Design Example User Guide for more details. |
| FEEDBACK_TAP | Defines the feedback tap for the PRBS pattern generator and checker. Refer to the JESD204B IP Core Design Example User Guide for more details. |