Arria® 10 SoC Boot User Guide

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ID 683735
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. Arria 10 SoC Boot User Guide
1. Arria 10 SoC Boot User Guide x
1.1. Boot Process 1.2. Boot Stages 1.3. Boot Devices 1.4. Second-Stage Boot Loader Support Package Generator Tool 1.5. Generating a Boot Loader with an External Flash Boot Device 1.6. Boot and FPGA Configuration 1.7. Boot Debugging 1.8. Appendix A: Building the UEFI Boot Loader 1.9. Revision History for Arria 10 SoC Boot User Guide
1.1. Boot Process x
1.1.1. Typical Boot Flow 1.1.2. Bare Metal Boot Flow 1.1.3. Custom Boot Loader
1.2. Boot Stages x
1.2.1. Reset 1.2.2. First Stage: Boot ROM 1.2.3. Second Stage: Boot Loader (U-Boot)
1.2.2. First Stage: Boot ROM x
1.2.2.1. Boot ROM Flow
1.2.3. Second Stage: Boot Loader (U-Boot) x
1.2.3.1. Second-Stage Boot Flow
1.2.3.1. Second-Stage Boot Flow x
1.2.3.1.1. Typical Boot Flow (Non-Secure) 1.2.3.1.2. Secure Boot Flow
1.3. Boot Devices x
1.3.1. Boot Select 1.3.2. Flash Memory Devices for Booting 1.3.3. Booting From FPGA
1.3.2. Flash Memory Devices for Booting x
1.3.2.1. Quad SPI Flash Devices 1.3.2.2. SD/MMC Flash Devices 1.3.2.3. NAND Flash Devices
1.4. Second-Stage Boot Loader Support Package Generator Tool x
1.4.1. Boot Loader Generation and Flow
1.4.1. Boot Loader Generation and Flow x
1.4.1.1. Step 1: Compiling the FPGA Design 1.4.1.2. Step 2: Hardware Hand-off Files 1.4.1.3. Step 3: Generating the Boot Loader Source 1.4.1.4. Boot Loader Generator Tool: BSP Editor
1.5. Generating a Boot Loader with an External Flash Boot Device x
1.5.1. Prerequisites 1.5.2. Boot Loader Generation Example Using an SD/MMC Controller 1.5.3. Boot Loader Generation Example Using a QSPI Flash Controller 1.5.4. Boot Loader Generation Example Using a NAND Flash Controller
1.7. Boot Debugging x
1.7.1. Cold Boot Debug 1.7.2. Warm Boot Debug 1.7.3. Using the Boot ROM and Boot Loader Debug Registers 1.7.4. Boot Flash Device Issues 1.7.5. HPS Boot Loader Debugging
1.8. Appendix A: Building the UEFI Boot Loader x
1.8.1. Prerequisites 1.8.2. Supported Compiler Toolchains 1.8.3. Obtaining the UEFI Source Code 1.8.4. Compiling the UEFI Source Code with the Linaro Tool Chain 1.8.5. Compiling the UEFI Source Code with the ARM Tool Chain 1.8.6. UEFI Generated Files
1. Arria 10 SoC Boot User Guide

1.2.2. First Stage: Boot ROM

The boot ROM code is 128 KB in size and located in on-chip ROM at addresses 0xFFFC0000 to 0xFFFDFFFF. The function of the boot ROM code is to determine the boot source, initialize the HPS after a reset, and jump to the second-stage boot loader. If the second-stage boot loader image has already been loaded from the flash memory to on-chip RAM, the boot ROM jumps to on-chip RAM location. The boot ROM performs the following actions to initialize the HPS:

  • Enables instruction cache, branch predictor, floating point unit, and NEON vector unit of CPU0
  • Sets up the level 4 (L4) watchdog 0 timer
  • Configures dedicated pins based on Boot Select (BSEL) settings
  • Initializes the flash controller to default settings
When booting from flash memory, the boot ROM code uses the top 32 KB of the on-chip RAM as data workspace. This area is reserved for the boot ROM code after a reset until the boot ROM code passes software control to second-stage boot loader. The maximum second-stage boot loader size is 208 KB with authentication and 224 KB without. For a warm boot from RAM or a boot from FPGA, the boot ROM code does not reserve the top 32 KB of the on-chip RAM, and the user may place user data in this area without being overwritten by the boot ROM.
Note: The boot ROM only initializes the portions within the 32 KB of on-chip RAM it uses. If ECC is required by the second-stage boot loader in on-chip RAM, then you should enable the security fuse that clears all RAMs on a cold reset. Refer to SoC Security chapter in the Arria 10 Hard Processor System Technical Reference Manual for more information on secure fuses.

The boot process begins when CPU0 exits from the reset state. The boot ROM code only executes on CPU0. CPU1 is held in reset until it is released by user software. When CPU0 exits from reset, it starts executing code at the reset exception address.

During boot ROM execution, the clock control fuse information is automatically sent to the Clock Manager, the memory control fuse information is automatically sent to the Reset Manager and all other fuse functions (authentication, encryption, private and public key source, hash functions) are stored in a memory-mapped location for boot code to read. In normal operation, the boot ROM is mapped at the reset exception address so code starts executing in the boot ROM.

When CPU0 exits the boot ROM code and starts executing user software, boot ROM access is disabled. The user software executing on CPU0 must map the user software exception vectors to 0x0 (which was previously mapped to the boot ROM exception vectors) and release CPU1 from reset, if required. When CPU1 is released from reset, CPU1 executes the user software exception instead of the boot ROM.

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