Arria 10 Transceiver Native PHY IP Core Release Notes

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ID 683744
Date 10/31/2016
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Document Table of Contents
Document Table of Contents x
1. Arria 10 Transceiver Native PHY IP Core Release Notes
1. Arria 10 Transceiver Native PHY IP Core Release Notes x
1.1. Arria 10 Transceiver Native PHY IP Core v15.1 Revision History 1.2. Arria 10 Transceiver Native PHY IP Core v15.0 Revision History 1.3. Arria 10 Transceiver Native PHY IP Core v14.1 Revision History 1.4. Arria 10 Transceiver Native PHY IP Core v14.0 Revision History 1.5. Arria 10 Transceiver Native PHY IP Core v13.1 Revision History
1. Arria 10 Transceiver Native PHY IP Core Release Notes

1.3. Arria 10 Transceiver Native PHY IP Core v14.1 Revision History

Table 4.  14.1 December 2014
Description Impact
Added support for multiple silicon revisions supported for ACDS 14.1 version of the Quartus II software. -
Added a new parameter for Interlaken protocol implementation called Enable Interlaken TX random disparity bit. When enabled, a random number is used as a disparity bit.
Changed the option "Manual (PLD controlled)" to "Manual (FPGA fabric controlled)" for the RX word aligner mode parameter. -
Changed the option "SATA" to "SATA/SAS" for PMA configuration rules parameter. -
Changed the descriptions of parameters CTLE adaptation mode and DFE adaptation mode. -
The Quartus II software v14.1 requires that you specify a device if your IP core targets the Arria 10 device family. If you do not specify your target Arria 10 device, the IP Upgrade tool insists that your IP core requires upgrade but does not clarify the reason. You must ensure that you specify a device for your v13.1 Arria 10 Edition or v14.0 Arria 10 Edition IP core variation and regenerate it in the Quartus II software v14.1.
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