Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683747
Date 6/22/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide

2.5.1. Internal Loopback Test

Run these steps to perform the internal loopback test:
  1. Reset the system. 
    sys_reset_digital_analog
  2. Display the clock frequency and PHY status. 
    chkphy_status
  3. Turn on the internal loopback test. 
    loop_on
  4. Display the clock frequency and PHY status. The rx_clk is set to 312.5 MHz and rx_pcs_ready is set to 1. 
    chkphy_status
  5. Start the packet generator.
    start_pkt_gen
  6. Stop the packet generator. 
    stop_pkt_gen
  7. Review the number of transmitted and received packets.
    chkmac_stats
  8. Tun off the internal loopback test.
    loop_off
Level Two Title