Mailbox Client Intel® FPGA IPs Release Notes

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ID 683754
Date 4/01/2024
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Document Table of Contents x
1. Mailbox Client Intel® FPGA IP Release Notes
1. Mailbox Client Intel® FPGA IP Release Notes x
1.1. Mailbox Client Intel® FPGA IP 1.2. Agilex 5 Mailbox Client Intel® FPGA IP 1.3. Mailbox Client Intel FPGA IP User Guide Archives
1.1. Mailbox Client Intel® FPGA IP x
1.1.1. Mailbox Client Intel® FPGA IP v22.0.0 1.1.2. Mailbox Client Intel® FPGA IP v21.0.0 1.1.3. Mailbox Client Intel® FPGA IP v20.2.1 1.1.4. Mailbox Client Intel® FPGA IP v20.2.0 1.1.5. Mailbox Client Intel® FPGA IP v20.1.2 1.1.6. Mailbox Client Intel® FPGA IP v20.1.1 1.1.7. Mailbox Client Intel® FPGA IP v20.1.0 1.1.8. Mailbox Client Intel® FPGA IP v20.0.2 1.1.9. Mailbox Client Intel® FPGA IP v20.0.0 1.1.10. Mailbox Client Intel® FPGA IP v19.3 1.1.11. Intel FPGA Stratix 10 Mailbox Client v17.1
1.2. Agilex 5 Mailbox Client Intel® FPGA IP x
1.2.1. Agilex 5 Mailbox Client Intel® FPGA IP v1.0.0
1. Mailbox Client Intel® FPGA IP Release Notes

1.1.8. Mailbox Client Intel® FPGA IP v20.0.2

Table 8.  v20.0.2 2021.03.29
Quartus® Prime Version Description Impact
21.1

Added support to reset Timer 1 and Timer 2 delay registers during the event of Mailbox Client Intel® FPGA IP reset assertion.

No impact in Timer 1 and Timer 2 registers usage in Quartus® Prime software version from 20.2 and 20.4.

You must regenerate the Mailbox Client Intel® FPGA IP when moving from Quartus® Prime software version 20.4 or earlier to Quartus® Prime software version 21.1.

Added support to enable the connection capability between Mailbox Client Intel® FPGA IP IRQ signal and Nios® II processor IRQ signal.

You must migrate to Quartus® Prime software version 21.1 and regenerate Mailbox Client Intel® FPGA IP to enable this feature.
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