AN 809: SerialLite III IP Core Feature and Interface Differences between Stratix 10, Arria 10, and Stratix V

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ID 683797
Date 6/19/2017
Public
Document Table of Contents
Document Table of Contents x
SerialLite III IP Core Feature and Interface Differences between Stratix® 10 and Arria® 10, and Stratix® V
SerialLite III IP Core Feature and Interface Differences between Stratix® 10 and Arria® 10, and Stratix® V x
Differences Summary Revision History
Differences x
Features Clocking IP Core GUI IP Core Signals
SerialLite III IP Core Feature and Interface Differences between Stratix® 10 and Arria® 10, and Stratix® V

IP Core GUI

Table 7.  IP Core GUI Differences between Stratix® 10, Arria® 10, and Stratix® V
Stratix® 10 Arria® 10 Stratix® V Comments
Adaptation FIFO partial full threshold N/A N/A Stratix® 10: Backpressure the upstream data through tx_ready port when the partial full flag triggers.
N/A N/A Device speed grade Transceiver speed grade.

Stratix® 10 and Arria® 10: N/A (user should refer to the transceiver PHY datasheet for the maximum data rate supported.)

Stratix® V: This is used to determine supported data rate ( Stratix® V IP parameter does not generate an error)

N/A N/A PLL type (CMU, ATX, fPLL) Stratix® 10 and Arria® 10: Transmitter (TX) PLL is instantiated outside the IP core.
Example Design Presets
  • Advanced_Clocking_Mode_6x12.5G
  • Advanced_Clocking_Mode_6x17.4G
  • Standard_Clocking_Mode_6x12.5G
  • Standard_Clocking_Mode_6x17.4G
  • Advanced Clocking Mode 2x10G
  • Advanced Clocking Mode 6x12.5G
  • Standard Clocking Mode 2x10G
  • Advanced Clocking Mode 6x12.5G
  • Advanced Clocking Mode 2x10G
  • Standard Clocking Mode 2x10G
 Presets in IP GUI supported for design example generation.
Related Information
Level Two Title