AN 294: Crosspoint Switch Matrices in Altera MAX Series

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ID 683806
Date 9/22/2014
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Document Table of Contents
Document Table of Contents x
1. Crosspoint Switch Matrices in Altera MAX Series
1. Crosspoint Switch Matrices in Altera MAX Series x
1.1. Crosspoint Switches Using Supported Altera Devices 1.2. Implementation 1.3. Document Revision History
1.1. Crosspoint Switches Using Supported Altera Devices x
1.1.1. 16 × 16 Crosspoint Switch 1.1.2. Customized Crosspoint Switch
1.1.1. 16 × 16 Crosspoint Switch x
1.1.1.1. 16 × 16 Crosspoint Switch Architecture 1.1.1.2. Signals 1.1.1.3. Switch Matrix 1.1.1.4. Address Decoder 1.1.1.5. Configuration 1.1.1.6. Crosspoint Switch Expansion
1.1.1.6. Crosspoint Switch Expansion x
1.1.1.6.1. Source Code Modification 1.1.1.6.2. Multiple Device Implementation
1.1.2. Customized Crosspoint Switch x
1.1.2.1. Customized Crosspoint Switch Architecture 1.1.2.2. Configuration
1.2. Implementation x
1.2.1. Design Example: 16 × 16 Crosspoint Switch 1.2.2. Design Example: Customized Crosspoint Switch
1.2.1. Design Example: 16 × 16 Crosspoint Switch x
1.2.1.1. Reference Design Files Hierarchy 1.2.1.2. Reference Design Files 1.2.1.3. Design Utilization 1.2.1.4. Crosspoint Switch Expansion 1.2.1.5. Design Verification
1.2.2. Design Example: Customized Crosspoint Switch x
1.2.2.1. Cutomized Crosspoint Switch Configuration 1.2.2.2. Design Utilization 1.2.2.3. Design Verification
1. Crosspoint Switch Matrices in Altera MAX Series

1.1.1.5. Configuration

Configuration is the main feature in a crosspoint switch. The configuration module consists of a double row register architecture, which allows reconfiguration of input to output connections during operation. Activation of the new configuration occurs with a single configuration pulse.

The switch matrix circuit is controlled by data in two sets of 16, 4-bit registers —LOAD REGISTERS and CONFIGURATION REGISTERS. You can use four bits of each register to store the input address that identifies the input which you can connect to a particular output. Table 3 shows the connection of an input to a particular output when you select a different input address.

Table 3.  Input Connection to a Specific Output
Input Address (Multiplexer Select Pin) [3..0] Output
0000 Input 0
0001 Input 1
0011 Input 2
0010 Input 3
0110 Input 4
0111 Input 5
0101 Input 6
0100 Input 7
1100 Input 8
1101 Input 9
1111 Input 10
1110 Input 11
1010 Input 12
1011 Input 13
1001 Input 14
1000 Input 15

You can select one of the 16, 4-bit registers in the first set of LOAD REGISTERS by placing a 4-bit word on the output address bus. You can place data that is written into the load register on the input address bus. The load register contains the 4-bit address of the input that connects to that output. The load register stores input data at the low-to-high transition of the load input pin with the chip-select (cs) signal set to high. The contents of the load registers are then transferred to the second set of CONFIGURATION REGISTERS at the low-to-high transition of the cnfg input signal with the cs signal set to high. This transition sets the state of the entire switch matrix to the chosen configuration.

Reset mode is also supported in this 16 × 16 crosspoint switch. When you assert the reset (res) signal (with cs set to high), the entire crosspoint switch is in its initial state where all outputs are connected to input0.

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