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1.1. Design Example Directory Structure
1.2. Simulation Design Example Components
1.3. Hardware Design Example Components
1.4. Generating the Design Example
1.5. Simulating the 25G Ethernet Intel FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the 25G Ethernet Intel FPGA IP Hardware Design Example
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2.3. 25G Ethernet Intel FPGA IP Design Example Registers
Word Offset |
Register Category |
---|---|
0x300–0xDFF |
25G Ethernet Intel FPGA IP core registers. |
0x4000–0x4C00 |
Intel® Arria® 10 dynamic reconfiguration registers. Register base address is 0x4000. |