Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

Download PDF
ID 683870
Date 10/05/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel FPGA Simulation Basics 3. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support 4. Synopsys VCS* and VCS MX Support 5. Aldec Active-HDL and Riviera-PRO Support 6. Cadence Xcelium* Parallel Simulator Support 7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Intel FPGA Simulation Basics x
2.1. Supported Simulators 2.2. Supported Simulation Levels 2.3. Supported Hardware Description Languages 2.4. Supported Simulation Flows 2.5. Preparing for Simulation 2.6. Running a Simulation (Custom Flow) 2.7. Intel FPGA Simulation Basics Revision History
2.5. Preparing for Simulation x
2.5.1. Compiling Simulation Model Libraries 2.5.2. Using The EDA Netlist Writer 2.5.3. Simulating Intel® FPGA IP Cores
2.5.3. Simulating Intel® FPGA IP Cores x
2.5.3.1. Generating IP Simulation Files 2.5.3.2. Scripting IP Simulation
2.5.3.2. Scripting IP Simulation x
2.5.3.2.1. Generating a Combined Simulator Setup Script ( Intel® Quartus® Prime Pro Edition) 2.5.3.2.2. Incorporating Simulator Setup Scripts from the Generated Template
3. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support x
3.1. Quick Start Example (ModelSim with Verilog) 3.2. Questa*-Intel® FPGA Edition, ModelSim, and Questa Simulator Guidelines 3.3. ModelSim Simulation Setup Script Example 3.4. Sourcing ModelSim* Simulator Setup Scripts 3.5. Unsupported Features 3.6. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support Revision History
3.2. Questa*-Intel® FPGA Edition, ModelSim, and Questa Simulator Guidelines x
3.2.1. Using Questa*-Intel® FPGA Edition Precompiled Libraries 3.2.2. Passing Parameter Information from Verilog HDL to VHDL 3.2.3. Viewing Simulation Messages 3.2.4. Generating Signal Activity Data for Power Analysis 3.2.5. Viewing Simulation Waveforms 3.2.6. Simulating with Questa*-Intel® FPGA Edition Waveform Editor
3.2.4. Generating Signal Activity Data for Power Analysis x
3.2.4.1. Generating Standard Delay Output for Power Analysis
4. Synopsys VCS* and VCS MX Support x
4.1. Quick Start Example (VCS with Verilog) 4.2. VCS and VCS MX Guidelines 4.3. VCS Simulation Setup Script Example 4.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 4.5. Sourcing Synopsys VCS* Simulator Setup Scripts 4.6. Synopsys VCS* and VCS MX Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
6. Cadence Xcelium* Parallel Simulator Support x
6.1. Using the Command-Line Interface 6.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 6.3. Cadence Xcelium* Parallel Simulator Support Revision History
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

2.5.3.2.1. Generating a Combined Simulator Setup Script ( Intel® Quartus® Prime Pro Edition)

You can run the Generate Simulator Setup Script for IP command to generate a combined simulator setup script.
Note: This feature is available in the Intel® Quartus® Prime Pro Edition software for all devices. This feature is available in the Intel® Quartus® Prime Standard Edition software for only Intel® Arria® 10 devices.

Source this combined script from a top-level simulation script. Click Tools > Generate Simulator Setup Script for IP (or use of the ip-setup-simulation utility at the command-line) to generate or update the combined scripts, after any of the following occur:

  • IP core initial generation or regeneration with new parameters
  • Intel® Quartus® Prime software version upgrade
  • IP core version upgrade
To generate a combined simulator setup script for all project IP cores for each simulator:
  1. Generate, regenerate, or upgrade one or more IP core. Refer to Generating IP Cores or Upgrading IP Cores.
  2. Click Tools > Generate Simulator Setup Script for IP (or run the ip-setup-simulation utility). Specify the Output Directory and library compilation options. Click OK to generate the file. By default, the files generate into the /<project directory>/<simulator>/ directory using relative paths.
  3. To incorporate the generated simulator setup script into your top-level simulation script, refer to the template section in the generated simulator setup script as a guide to creating a top-level script:
    1. Copy the specified template sections from the simulator-specific generated scripts and paste them into a new top-level file.
    2. Remove the comments at the beginning of each line from the copied template sections.
    3. Specify the customizations you require to match your design simulation requirements, for example:
      • Specify the TOP_LEVEL_NAME variable to the design’s simulation top-level file. The top-level entity of your simulation is often a testbench that instantiates your design. Then, your design instantiates IP cores or Platform Designer systems. Set the value of TOP_LEVEL_NAME to the top-level entity.
      • If necessary, set the QSYS_SIMDIR variable to point to the location of the generated IP simulation files.
      • Compile the top-level HDL file (for example, a test program) and all other files in the design.
      • Specify any other changes, such as using the grep command-line utility to search a transcript file for error signatures, or e-mail a report.
  4. Re-run Tools > Generate Simulator Setup Script for IP (or ip-setup-simulation) after regeneration of an IP variation.
    Table 5.  Simulation Script Utilities
    Utility Syntax
    ip-setup-simulation generates a combined, version-independent simulation script for all Intel® FPGA IP cores in your project. The command also automates regeneration of the script after upgrading software or IP versions. Use the compile-to-work option to compile all simulation files into a single work library if your simulation environment requires. Use the --use-relative-paths option to use relative paths whenever possible. 
    ip-setup-simulation
 --quartus-project=<my proj>
 --output-directory=<my_dir>
 --use-relative-paths
 --compile-to-work

    --use-relative-paths and --compile-to-work are optional. For command-line help listing all options for these executables, type: <utility name> --help.

    ip-make-simscript generates a combined simulation script for all IP cores that you specify on the command line. Specify one or more .spd files and an output directory in the command. Running the script compiles IP simulation models into various simulation libraries. 
    ip-make-simscript 
 --spd=<ipA.spd,ipB.spd> 
 --output-directory=<directory>
    ip-make-simscript generates a combined simulation script for all IP cores and subsystems that you specify on the command line. 
    ip-make-simscript 
--system-files=<ipA.ip, ipB.ip> 
--output-directory=<directory>
Level Two Title