DisplayPort Stratix® 10 FPGA IP Design Example User Guide

ID 683887
Date 4/10/2024
Public
Document Table of Contents

2.2.2. Stratix® 10 DisplayPort SST RX-only Design Features

This RX-only design example demonstrates the transmission of a single video stream from DisplayPort sink with Pixel CLock Recovery (PCR).
Figure 8.  Stratix® 10 DisplayPort SST RX-only
  • To generate this RX-only variant, turn on the DisplayPort sink RX SUPPORT DP and the DisplayPort source TX SUPPORT DP parameters.
  • This variant uses the standard VSYNC/HSYNC/DE video interface, while the DisplayPort source TX SUPPORT IM ENABLE parameter is turned off.
  • The IOPLL drives video clock at a fixed frequency (in this case, 300 MHz by default).
  • If you configure the DisplayPort sink MAX LINK RATE parameter to HBR3 or MAX LINK RATE parameter to HBR2 and PIXELS PER CLOCK to DUAL, the video clock runs at 300 MHz to support 4Kp60 pixel rate (594/2 = 297 MHz). Otherwise, the video clock runs at 160 MHz.
  • The DisplayPort sink receives video from an external video source such as a GPU and decodes it for the parallel video interface.
  • The design uses the pixel recovery clock (PCR) to recover the pixel clock according to the received MSA information from the sink and converts the RX parallel video interface to the standard VSYNC/HSYNC/DE interface.