External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

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ID 710283
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to this Handbook 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to this Handbook x
1.1. Introduction to Memory Solutions 1.2. Protocol Support Matrix 1.3. Document Revision History
2. Recommended Design Flow x
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces x
2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory x
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. Memory Selection 3.8. Example of High-Speed Memory in Embedded Processor 3.9. Example of High-Speed Memory in Telecom 3.10. Document Revision History
4. Selecting Your FPGA Device x
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection x
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts
1. Introduction to this Handbook
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

2.1.2. Selecting Your FPGA

Different Intel® FPGA devices support different memory types; not all Intel® devices support all memory protocols and configurations. Before you start your design, you must select an Intel® device, which supports the memory standard and configurations you plan to use.
  1. Determine the I/O interface that best suits your design requirements.
  2. Determine whether your design requires read or write levelling circuitry.
    Some Intel® FPGAs support read and write levelling, to apply or remove skew from an interface on a DQS group basis.
  3. Determine whether your design requires dynamic calibrated on-chip termination (OCT).
    Some Intel® FPGAs provide dynamic OCT, allowing a specified series termination to be enabled during writes and parallel termination to be enabled during reads. Dynamic OCT can simplify your PCB termination schemes.
  4. Consult the Intel® FPGA Product Selector to find the Intel® FPGA that provides the combination of features that your design requires.
  5. Refer to the Ordering Information section of the appropriate device handbook, to determine the correct ordering code for the device that you require. Consider the following characteristics in determining the correct ordering code:
    • Speed grade: Affects performance, timing closure, and power consumption. The device with the smallest speed grade number is the fastest device.
    • Operating temperature: Intel® FPGAs are divided into the following temperature categories:
      • Commercial grade—Used for all device families. Operating temperature ranges from 0 degreec C to 85 degrees C.
      • Industrial grade—Used for all device families. Operating temperature ranges from -40 degreec C to 100 degrees C.
      • Military grade—Used for Stratix® IV device families. Operating temperature ranges from -55 degree C to 125 degrees C.
      • Automotive grade—Used for Cyclone® V device families. Operating temperature ranges from -40 degreec C to 125 degrees C.
    • Package size: Refers to the physical size of the FPGA device, and corresponds to the number of pins. For example, the package size for the smallest Stratix IV device is 29 mm x 29 mm, categorized under the F780 package option, where F780 refers to a device with 780 pins.
    • Device density: Refers to the number of logic elements, such as PLLs and memory blocks. Devices with higher density contain more logic elements in less area.
    • I/O pin counts: The number of I/O pins required on an FPGA depends on the memory standard, the number of memory interfaces, and the memory data width.
Tip: For additional, device-specific, information, refer to the External Memory Interface chapter in the device handbook for your Intel® device.
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