F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 4/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Enabled Auto-Negotiation and Link Training 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Enabled Auto-Negotiation and Link Training x
4.1. Ethernet Multirate Design Example with Enabled AN/LT: Functional Description
4.1. Ethernet Multirate Design Example with Enabled AN/LT: Functional Description x
4.1.1. Ethernet Multirate Design Example with Enabled AN/LT: Simulation Testbench 4.1.2. Ethernet Multirate Hardware Design Example with Enabled AN/LT
4.1.2. Ethernet Multirate Hardware Design Example with Enabled AN/LT x
4.1.2.1. Ethernet Multirate Design Example with Enabled AN/LT: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Enabled Auto-Negotiation and Link Training
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

1.2.2. Ethernet Multirate Design Example Parameters

Figure 4. Ethernet Multirate Example Design Tab
Table 3.  Ethernet Multirate Design Example Parameters
Parameters Value Description
Select Protocol/mode

Ethernet

 Select the IP protocol for dynamic reconfiguration.
Select Base Variant

25G-1

25G-1 PTP

100G-4

100G-4 PTP

400G-8

400G-8 PTP

FHT 400G-4

 Select the configuration of base variant for dynamic reconfiguration.
Example Design Files Simulation

Synthesis

 Simulation option generates the testbench and compilation-only project. Synthesis option generates the hardware design example.
Generated File Format Verilog

VHDL

 Select the HDL files format. If you select VHDL, you must simulate the testbench with a mixed-language simulator.
Target Development Kit None

Agilex™ 7 I-Series Transceiver-SoC Development Kit DK-SI-AGI027FA

Agilex™ 7 I-Series Transceiver-SoC Development Kit DK-SI-AGI027FB

Target development kit option specifies the target development kit used to generate the project.
Auto-Negotiation and Link Training Options
Enable auto-negotiation and link training

On

Off

 Enables auto-negotiation and link training for the Ethernet port.

When the design example is generated using dynamic reconfiguration with ANLT IP enabled, the design example automatically instantiates the F-Tile Auto-Negotiation and Link Training FPGA IP.

Enable auto-negotiation and link training optimized simulation

On

Off

When enabled, reduces the simulation time as much as possible while still maintaining the basic ANLT protocol and be able to send and receive Ethernet frames.

Level Two Title