Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 12/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Installation and Setup 3. Getting Started with RiscFree* IDE 4. Debug Setup for Nios® V Processor System 5. Debug Setup for Arm* Hard Processor System 6. Debugging with RiscFree* IDE 7. Debugging with Command-Line Interface 8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Intel® Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Installation and Setup x
2.1. Bundled Installation with the Intel® Quartus® Prime Software 2.2. Standalone Installation
2.2. Standalone Installation x
2.2.1. Standalone Installation with Supported Intel® Quartus® Prime Software 2.2.2. Standalone Installation with the Intel® Quartus® Prime Programmer and Tools
3. Getting Started with RiscFree* IDE x
3.1. Graphical User Interface 3.2. Command Line Interface 3.3. Ashling* RiscFree* IDE for Intel® FPGAs Interaction with Intel® Simics® Simulator for Intel® FPGAs
4. Debug Setup for Nios® V Processor System x
4.1. Importing Nios® V Processor Project 4.2. Building Nios® V Processor Project 4.3. Setting Debug Configurations and Downloading Nios® V Processor Project Using RiscFree* IDE
5. Debug Setup for Arm* Hard Processor System x
5.1. Pre-requisite for Debugging Arm* HPS Project 5.2. Importing Arm* HPS Project 5.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
6. Debugging with RiscFree* IDE x
6.1. Debug Features in RiscFree* IDE 6.2. Processor System Debug 6.3. Heterogeneous Multicore Debug 6.4. Debugging µC/OS-II Application 6.5. Debugging FreeRTOS Application 6.6. Debugging Zephyr Application 6.7. Arm* HPS On-Chip Trace 6.8. Debugging the Arm* Linux Kernel 6.9. Debugging Target Software in an Intel® Simics Simulator Session
6.1. Debug Features in RiscFree* IDE x
6.1.1. Viewing Global Variables 6.1.2. Launching Memory Browser 6.1.3. Debugger Console 6.1.4. Specifying the SVD File 6.1.5. Breakpoint Settings 6.1.6. JTAG UART Output Terminal
6.2. Processor System Debug x
6.2.1. GUI for Debugging
6.3. Heterogeneous Multicore Debug x
6.3.1. Importing Nios® V Processor and Arm* HPS Projects 6.3.2. Setting Core Configuration
6.7. Arm* HPS On-Chip Trace x
6.7.1. Trace Bar 6.7.2. Trace View
6.8. Debugging the Arm* Linux Kernel x
6.8.1. Preparing Linux for Kernel Debugging 6.8.2. Debugging the Arm* HPS Linux Kernel
7. Debugging with Command-Line Interface x
7.1. Running Ashling* GBD Server 7.2. Running GDB 7.3. Nios® V Processor Example 7.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Debugging with Command-Line Interface
8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

6.7. Arm* HPS On-Chip Trace

You can configure and capture the Arm HPS On-Chip Trace with Intel® FPGA Download Cable II. The following table shows the Arm* trace sources that generate instruction trace:
Table 11.  Arm Trace Source
Arm Trace Source Encoding Type Description Supported Device
Program Trace Macrocell (PTM) PTM A real-time trace module providing instruction tracing of a processor
  • Intel® Arria® 10
  • Intel® Cyclone® V
Embedded Trace Macrocell (ETM) ETMv4 The Arm trace source that captures data and instruction trace
  • Intel Agilex® 7
  • Intel® Stratix® 10
Follow the steps to enable and configure the Trace feature:
  1. Launch Ashling Arm Hardware Debugging, and click the Trace tab.
    Figure 33. Trace Tab
  2. Click the Enable trace checkbox to enable the trace selected settings. The Trace architecture defaults to Arm Coresight. The trace selected settings appear in the following tab:
    1. Capture Settings
    2. Producer Settings
    3. Trigger/Filter Settings
      Figure 34. Capture Settings Sub-Tab
  3. Under the Capture Settings tab, set this settings:
    1. Select On-chip.
    2. Select one of the following Device Buffer Configuration:
      1. Embedded Trace FIFO (ETF) — stores trace data in small and fixed size trace buffer.
      2. Embedded Trace Router (ETR) — routes the trace data to the system memory. You need to specify the RAM location and Size .
    3. Wrap-around — enables overwriting old trace data with the new trace data when the trace buffer is full.
      Note: Wrap-around is optional. If you do not select Wrap-around, trace capture stops when the trace buffer is full.
  4. Under Producer Settings tab, set this settings:
    1. Select your preferred settings:
      1. Cycle Accurate Trace — captures trace on all cycles even if there is no trace to output on that cycle.
      2. Enable context ID — enables the tracing of the ASID and the current process ID.
      3. Enable timestamp — enables timestamps in your trace.
    2. For Encoding type, you can select ETMv4 or PTM. Refer to Table Arm Trace Source for more details.
      Note: ETMv3 is an older version of ETMv4 and not supported by Intel devices.
      Figure 35. Producer Settings Sub-tab
  5. Under Trigger/Filter Settings tab, click the Enable trigger checkbox.
    Figure 36. Trigger/Filter Settings Tab
  6. Click Add to bring up the Add Trigger dialog box as shown below:
    Figure 37. Add Trigger Dialog Box
    1. For Trace action, choose one of the following options:
      1. Trace include— limits trace to the selected address range
      2. Trace exclude— excludes trace from the selected address range
      3. Trace start point— starts tracing when the selected address is executed
      4. Trace stop point— stops tracing when the selected address is executed
    2. For Core, use the same core that you select in Debugger tab.
    3. For Access type, select the only available option — Instruction execution as instruction trace and to support trigger.
  7. Once you complete the configuration, click Debug.
  8. Open Trace view via Window > Show > View > Other > Debug > Trace. Click Fetch, decode and populate trace data button on the top right of the window to fetch trace data from the target and display in the Trace view as shown below.
    Figure 38. Trace View

Section Content
Trace Bar
Trace View

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