AN 987: Static Update Partial Reconfiguration Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

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ID 749443
Date 10/24/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Static Update Partial Reconfiguration Tutorial for Intel® Agilex™ F-Series FPGA Development Board
2. Static Update Partial Reconfiguration Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
2.1. Tutorial Requirements 2.2. Reference Design Overview 2.3. Static Update Region Overview 2.4. Download Reference Design Files 2.5. Reference Design Walkthrough 2.6. Document Revision History of AN 987: Static Update Partial Reconfiguration Tutorial Revision History
2.5. Reference Design Walkthrough x
2.5.1. Step 1: Getting Started 2.5.2. Step 2: Create Design Partitions 2.5.3. Step 3: Allocate Placement and Routing Regions 2.5.4. Step 4: Define Personas 2.5.5. Step 5: Create Revisions 2.5.6. Step 6: Compile the Base Revision 2.5.7. Step 7: Set Up PR Implementation Revisions 2.5.8. Step 8: Change the SUPR Logic 2.5.9. Step 9: Program the Board 2.5.10. Modifying the SUPR Partition
2.5.5. Step 5: Create Revisions x
2.5.5.1. Setting the Base Revision 2.5.5.2. Creating Implementation Revisions
2.5.9. Step 9: Program the Board x
2.5.9.1. Troubleshooting PR Programming Errors
1. Answers to Top FAQs
2. Static Update Partial Reconfiguration Tutorial for Intel® Agilex™ F-Series FPGA Development Board

2.2. Reference Design Overview

This reference design consists of one, 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and then connects the output to four LEDs on the board. Selecting the output from the counter bits, in a specific sequence, causes the LEDs to blink at a specific frequency. The top_counter module is the SUPR region.
Figure 1. Flat Reference Design
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