AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 2/12/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.3.3.2. TX MRD TLP

The register indicates number of memory read TLPs transmitted by the IP.

Default Value: 0x0000_0000

Table 81.  TX MRD TLP Registers
Register Name Bit Attribute User Side Description
TX MRD TLP 31-0 RW1C Number of Memory Read TLPs