Cyclone® V GT FPGA Development Kit User Guide

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ID 792833
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Kit Features 2. Getting Started 3. Software Installation 4. Development Board Setup 5. Board Update Portal 6. Board Test System 7. Document Revision History for Cyclone® V GT FPGA Development Kit User Guide A. Programming the Flash Memory Device B. Additional Information
1. Kit Features x
1.1. Hardware 1.2. Software
1.2. Software x
1.2.1. Intel® Quartus® Prime Software 1.2.2. Cyclone® V GT FPGA Development Kit Installer
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. References for Getting Started
3. Software Installation x
3.1. Installing the Intel® Quartus® Prime Subscription Edition Software 3.2. Activating Your License 3.3. Installing the Development Kit 3.4. Installing the Intel® FPGA Download Cable II Driver
4. Development Board Setup x
4.1. Setting Up the Board 4.2. Factory Default Switch and Jumper Settings 4.3. Configuring the MAX® V Device to Program EPCQ 4.4. Restoring the MAX® V CPLD to the Factory Settings 4.5. Restoring the Flash Device to the Factory Settings 4.6. Configuring the FPGA Using the Intel® Quartus® Prime Programmer
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page 5.2. Using the Board Update Portal to Write User Designs
6. Board Test System x
6.1. Preparing to Run the Board Test System 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. The Power Monitor 6.5. The Clock Control
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The DDR3x40 and DDR3x64 Tabs 6.3.6. The HSMA Tab 6.3.7. The HSMB Tab
6.3.2. The System Info Tab x
6.3.2.1. Power Tree 6.3.2.2. Power Monitor 6.3.2.3. Board Information 6.3.2.4. MAX® V Registers 6.3.2.5. JTAG Chain
6.3.3. The GPIO Tab x
6.3.3.1. Character LCD and Display 6.3.3.2. User DIP Switches 6.3.3.3. User LEDs 6.3.3.4. Push Buttons
6.3.4. The Flash Tab x
6.3.4.1. Read and Start Address 6.3.4.2. Range 6.3.4.3. Write 6.3.4.4. CFI Query 6.3.4.5. Reset 6.3.4.6. Erase 6.3.4.7. Flash Memory Table and Flash Memory Map
6.3.5. The DDR3x40 and DDR3x64 Tabs x
6.3.5.1. Start 6.3.5.2. Stop 6.3.5.3. Performance Indicators 6.3.5.4. Error Control 6.3.5.5. Number of Addresses to Write and Read
6.3.6. The HSMA Tab x
6.3.6.1. Start, Stop 6.3.6.2. XCRV, LVDS, CMOS
6.3.7. The HSMB Tab x
6.3.7.1. Start, Stop 6.3.7.2. XCRV and CMOS
6.4. The Power Monitor x
6.4.1. Power Monitor Features 6.4.2. Power Monitor Controls
6.4.2. Power Monitor Controls x
6.4.2.1. General Information 6.4.2.2. Power Information 6.4.2.3. Power Graph 6.4.2.4. Graph Settings 6.4.2.5. Reset
6.5. The Clock Control x
6.5.1. Clock Control Features 6.5.2. Clock Control Controls
6.5.2. Clock Control Controls x
6.5.2.1. Serial Port Registers 6.5.2.2. fXTAL 6.5.2.3. Target Frequency 6.5.2.4. Clear 6.5.2.5. Set New Frequency
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios® II EDS A.4. Converting Additional Files A.5. Programming Flash Memory Using the Nios® II EDS A.6. Programming Flash Memory Using the Board Update Portal
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Kit Features
2. Getting Started
3. Software Installation
4. Development Board Setup
5. Board Update Portal
6. Board Test System
7. Document Revision History for Cyclone® V GT FPGA Development Kit User Guide
A. Programming the Flash Memory Device
B. Additional Information

6.3.6.2. XCRV, LVDS, CMOS

The XCRV, LVDS, CMOS groups display the following status information during the loopback test:

Data rate—Displays the current data rate in megabytes per second (Mbps).

Freq—Displays the data rate frequency in MHz which is equivalent to Mbps.

Bits—Displays the number of bits transmitted since clicking Start.

Inserted errors—Displays the number of errors inserted by clicking Insert Error button.

Detected errors—Displays the number of bit errors detected by the error checking circuitry.

BER—Displays the bit error rate of the interface.

Status
  • PLL lock—Displays Yes if the PLL is locked.
  • Pattern Sync—Displays Yes if the receiver has detected the input data pattern.

Start—Starts the PRBS data test and begins to monitor and update screen with live test results.

Stop—Stops the PRBS data test.

Insert Error—Inserts an error into a data stream that is detected by the receiver when in loopback mode. With the Insert Error, there are differences among the three ports:
  • XCVR—Inserts 4 errors at 1 click.
  • LVDS—Inserts 3 errors at 1 click.
  • CMOS—Inserts 1 error at 1 click.

Clear—Clears the Detected errors counter.

PMA Setting—Only available for the XCVR test. This control allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:
  • Serial Loopback—Routes the selected TX output signal back to the RX input signal on-chip to verify operation without using an external loopback board.
  • VOD—Specifies the voltage output differential of the transmitter buffer.
  • Pre-emphasis tap
  • Pre—Not available.
    • First post—Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.

      Second post—Not available.

  • Equalizer—Specifies the setting for the receiver equalizer.
  • DC gain—Specifies the DC portion of the receiver equalizer.
Data Type—Specifies the type of data contained in the transactions. The following data types are available for analysis:
  • PRBS7—Pseudo-random 7-bit sequences
  • PRBS15—Pseudo-random 15-bit sequences
  • PRBS23—Pseudo-random 23-bit sequences
  • PRBS31—Pseudo-random 31-bit sequences
  • HF—Highest frequency divide-by-4 data pattern 10101010
  • LF—Lowest frequency divide-by-4 data pattern 11110000
Level Two Title