Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813775
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs 7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
CvP Initialization Mode CvP Update Mode 1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs
7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

1.3. CvP Modes

The CvP configuration scheme supports the following modes:

  • CvP Initialization mode
  • CvP Update mode

CvP Initialization Mode

This mode configures the CvP PCIe* core using the peripheral image of the FPGA through the on-board configuration device. Subsequently, configures the core fabric and all GPIOs that are not dedicated for PERST# signaling through the PCIe* link.

Benefits of using CvP Initialization mode include:

  • Satisfying the PCIe* wake-up time requirement
  • Saving cost by storing the core image in the host memory

CvP Update Mode

The CvP update mode is available after the FPGA enters user mode. You can configure the device through full chip configuration or CvP initialization initially to bring the device into user mode. In user mode, the PCIe* link is available for normal PCIe* applications as well as to perform an FPGA core image update.

The CvP update mode uses the same process as root partition reuse in block-based design, which allows you to reuse the device periphery.

Choose this mode if you want to update the core image for any of the following reasons:

  • To change or modify core FPGA logic functionality
  • To perform standard updates as part of a release process
  • To customize core processing for different components that are part of a complex system
Table 1.  CvP Supported Modes for Agilex™ 5 FPGAs
Note: The Agilex™ 5 FPGA supports monolithic transceiver integrated High-speed Serdes IO (HSSI) Subsystem that includes PCIe Hard IP. The hardware specifications are preliminary, pending the full silicon verification.
Device Supported PCIe Version
A5E 008B

PCIe* 4.0 x1

PCIe* 4.0 x2

PCIe* 4.0 x4

Note:

  1. You can only select PCIe* 3.0 and PCIe* 4.0 in PCIe* Hard IP1, but the host can down-train the link to PCIe* 1.0, PCIe* 2.0, and PCIe 3.0, if necessary.

  2. PCIe* x4 controller link width can be configured as X1, X2, or X4.
  3. PCIe* 4.0 is supported for Agilex™ 5 devices with speed grade -4S. PCIe* 4.0 is not supported for Agilex™ 5 devices with speed grades -5S and -6S.
A5E 013B
A5E 043B
A5E 052B
A5E 065B
A5E 013A
A5E 043A
A5E 052A
A5E 065A

Section Content
CvP Limitations

1 The full silicon has been validated for PCIe* 3.0 and PCIe* 4.0, but not for PCIe* 1.0 and PCIe* 2.0.
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