Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 5/08/2024
Public
Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL* FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Document Revision History for Migrating OpenCL FPGA Designs to SYCL* x
Notices and Disclaimers
Migrating OpenCL™ FPGA Designs to SYCL*
FPGA Design Flow
Modify Your Design
Flags, Attributes, Directives, and Extensions
Histogram Design Example Walkthrough
Additional Information
Document Revision History for Migrating OpenCL FPGA Designs to SYCL*

FPGA Design Flow

Similar to OpenCL, SYCL* supports both online and offline compilation for non-FPGA targets. However, for FPGA hardware, only offline kernel compilation is supported. This is because the device binary generation process for FPGA hardware is computationally intensive and time-consuming, making online (just-in-time) compilation impractical. For this reason, Intel® oneAPI DPC++/C++ Compiler only supports offline (ahead-of-time) kernel compilation. As longer compile times impede your productivity, the compiler provides several mechanisms that enable you to target an FPGA and iterate quickly on your designs.

FPGA Design Flow Summary
OpenCL SYCL

The offline compiler in the Intel® FPGA SDK for OpenCL can create your FPGA programming image file in a single or multistep process. The following topics in the Intel FPGA SDK for OpenCL Pro Edition: Programming Guide describe these processes in detail:

Intel® oneAPI DPC++/C++ Compiler in the Intel oneAPI Base Toolkit supports multistep compilation for creating your FPGA programming image file. See Types of SYCL FPGA Compilation in the Intel® oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs for detailed information.
NOTE:

You need the Intel® oneAPI Base Toolkit to compile for FPGA emulation or optimization report generation. However, you must install the Intel® Quartus® Prime Pro software and BSPs for simulation or hardware compilation. See Intel FPGA development flow web page and Installation Guide for Intel® oneAPI Toolkits for more information.

The following table lists design flows with commands for OpenCL and SYCL:

Design Flow with Commands

Design Flow

OpenCL

SYCL

Comments

Emulation

(seconds)

aoc -march=emulator <your_kernel_filename>.cl

icpx -fsycl -fintelfpga <your single-source program>.cpp

The SYCL program must use the fpga_emulator_selector device selector.

See Emulate Your Design section in the Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs for additional information.

Simulation

(minutes)

aoc -march=simulator -ghdl -board=<board_name><your_kernel_filename>.cl

icpx -fsycl -fintelfpga -Xssimulation <your single-source program>.cpp

See Evaluate Your Kernel Through Simulation section in the Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs for additional information.

Optimization report

(minutes)

aoc -c <your_kernel_filename>.cl -report

aoc -rtl <your_kernel_filename>.cl

icpx -fsycl -fintelfpga -Xshardware -fsycl-link=early <your single-source program>.cpp

 See Review the FPGA Optimization Report section in the Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs for detailed information about the reports.

One-step compilation to hardware image

(hours)

aoc <your_kernel_filename>.cl [-report]

icpx -fsycl -fintelfpga -Xshardware <your_single-source_program>.cpp

 The -Xshardware flag compiles to FPGA hardware using the Quartus® Prime Pro software.

See Install the Quartus® Prime Pro Software section in the Intel® oneAPI Toolkits Installation Guide for Linux* OS for information.

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