Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 5/08/2024
Public
Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL* FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Document Revision History for Migrating OpenCL FPGA Designs to SYCL* x
Notices and Disclaimers
Migrating OpenCL™ FPGA Designs to SYCL*
FPGA Design Flow
Modify Your Design
Flags, Attributes, Directives, and Extensions
Histogram Design Example Walkthrough
Additional Information
Document Revision History for Migrating OpenCL FPGA Designs to SYCL*

Prerequisites

This guide assumes the following:

  • You have experience working with OpenCL™ for FPGAs.
  • You have experience programming with C++, especially namespaces, exceptions, templates, lambdas, and functors.
  • You are familiar with SYCL* concepts and application programming interfaces (APIs).
  • You have a preliminary knowledge of programming SYCL applications for CPU, GPU, FPGA, or AI accelerators.

If you are new to SYCL, consider reviewing the following resources first:

  • Access oneAPI Samples for FPGAs on GitHub and follow all Tier 1 tutorials and the explicit_data_movement tutorial in Tier 2.
  • For guidance on leveraging the functionalities of data parallel C++ (DPC++) and the SYCL* cross-platform abstraction layer to optimize your FPGA design, refer to the Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs.
  • For a high-level overview of oneAPI, Intel oneAPI Toolkits, and related resources, refer to the Intel® oneAPI Programming Guide.
  • To achieve the highest performance with your SYCL application for FPGAs, you should be familiar with FPGA hardware and understand the compiler optimizations that convert and map your design to FPGAs. Many of these concepts are the same, whether the FPGA design is written in SYCL or OpenCL, so your experience with Intel® FPGA SDK for OpenCL™ carries over. For more information, refer to the Introduction To FPGA Design Concepts in Intel® oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs.

For additional information about the SYCL concepts, read the open-access book Data Parallel C++: Programming Accelerated Systems Using C++ and SYCL*. You can also consult the SYCL 2020 Specification.

Parent topic: Migrating OpenCL™ FPGA Designs to SYCL*
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