5G LDPC Intel® FPGA IP User Guide

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ID 683107
Date 3/29/2021
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC Intel® FPGA IP 4. 5G LDPC Intel® FPGA IP Functional Description 5. Parameter Optimization for the 5G LDPC IP 6. 5G LDPC IP User Guide Document Archive 7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide
1. About the 5G LDPC Intel® FPGA IP x
1.1. 5G LDPC Intel® FPGA IP Features 1.2. 5G LDPC Intel® FPGA IP Device Family Support 1.3. 5G LDPC IP Release Information 1.4. 5G LDPC IP Performance and Resource Utilization
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC IP IP Timeout Behavior
3. Designing with the 5G LDPC Intel® FPGA IP x
3.1. Generating a 5G LDPC Intel® FPGA IP 3.2. Simulating the 5G LDPC IP RTL 3.3. 5G LDPC Simulation Results
4. 5G LDPC Intel® FPGA IP Functional Description x
4.1. 5G LDPC Decoder 4.2. 5G LDPC Encoder 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1. 5G LDPC Decoder x
4.1.1. 5G LDPC Decoder Signals 4.1.2. 5G LDPC Decoder Data Formats 4.1.3. 5G LDPC IP Decoder Parameters
4.2. 5G LDPC Encoder x
4.2.1. 5G LDPC Encoder Signals 4.2.2. 5G LDPC Encoder Data Formats
5. Parameter Optimization for the 5G LDPC IP x
5.1. C++ and MATLAB Software Models
5.1. C++ and MATLAB Software Models x
5.1.1. Running the 5G LDPC IP C++ Models 5.1.2. Running the 5G LDPC Decoder and Encoder MATLAB Model in the Design Example
1. About the 5G LDPC Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC Intel® FPGA IP
4. 5G LDPC Intel® FPGA IP Functional Description
5. Parameter Optimization for the 5G LDPC IP
6. 5G LDPC IP User Guide Document Archive
7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide

4.2.1. 5G LDPC Encoder Signals

Figure 14. Encoder Signals
Table 20.  Encoder Interface Signals

Signals names beginning with msg_ are in the input interface to the encoder IP; signal names beginning with cw_ are in the output interface from the encoder IP (except for msg_enc_ready). Both interfaces comply with the Avalon® -ST specification. The encoder can backpressure the design by deasserting a ready signal on the input interface, but the design cannot backpressure the encoder.

Name Direction Description
clk Input Clocks the 5G LDPC encoder IP signals and internal transitions.
rst_n Input Active low, asynchronous reset signal for 5G LDPC encoder IP. Asserting this signal for one full clock cycle is sufficient to ensure the reset process initiates.
Name Direction Description
msg_vld Input Qualifies the msg data signal. When msg_vld is not asserted, the encoder stops processing input until you reassert the msg_vld signal.

If the encoder deasserts the msg_enc_rdy signal, the upstream source must maintain the current value on msg_vld.

msg_sop Input Marks the start of an incoming packet.
msg_eop Input Marks the end of an incoming packet.
msg_enc_rdy Output Indicates that the encoder is ready to receive data on the current clock cycle. The encoder can backpressure incoming data by deasserting this signal.

The readyLatency for this signal is 0: the IP can read valid input data in the same clock cycle in which it raises this signal. Refer to the Avalon Interface Specifications for the description of this Avalon-ST interface property.

msg[383:0] Input Data input. The encoder processes this input only when the upstream source asserts the msg_vld signal and the IP asserts the msg_enc_rdy signal. If the encoder deasserts the msg_enc_rdy signal, the upstream source must maintain the current value on msg.
msg_mode[11:0] Input

This signal must be valid for the current information block when the upstream source asserts msg_sop.

  • [5:0] are Z
  • [8:6] are Code Rate
  • [9] is Base Graph [0=BG1, 1=BG2]
  • [11:10] are Kb
Name Direction Description
cw_vld Output The encoder asserts this signal when cw holds valid data.
cw_sop Output The encoder asserts this signal to mark the start of a packet.
cw_eop Output The encoder asserts this signal to mark the end of a packet.
cw[383:0] Output Data output. When the encoder sends valid data on this bus, it asserts the cw_vld signal.
cw_mode[11:0] Output The lifting size of the transmission block. The encoder drives this bus with the value it receives on the input bus msg_mode for the same information block.

This signal is valid when cw_sop is asserted.

Figure 15. Example 5G LDPC Encoder Input Timing DiagramThis timing diagram shows an example transaction on the encoder input interface. msg_mode[11:0] = {kb[1:0], bg[0], cr[2:0], z_ind[5:0]}. Refer to the Avalon Interface Specifications for information about the required behavior of the ready, valid, sop, eop, and data signals on this Avalon® -ST interface.
Figure 16.  5G LDPC Encoder Output Timing Diagram

The 5G LDPC encoder does not support backpressure on the output interface.

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