Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

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ID 683149
Date 8/18/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview x
1.1. Intel® Stratix® 10 MX Devices 1.2. Innovations in Intel® Stratix® 10 MX Devices 1.3. Intel® Stratix® 10 MX Features Summary 1.4. Intel® Stratix® 10 MX Block Diagram 1.5. Intel® Stratix® 10 MX Family Plan 1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.7. Intel® Hyperflex™ Core Architecture 1.8. Heterogeneous 3D SiP Transceiver Tiles 1.9. Intel® Stratix® 10 MX Transceivers 1.10. PCI Express Gen1/Gen2/Gen3 Hard IP 1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP 1.12. 10G Ethernet Hard IP 1.13. Interlaken PCS Hard IP 1.14. External Memory and General Purpose I/O 1.15. Adaptive Logic Module (ALM) 1.16. Core Clocking 1.17. Fractional Synthesis PLLs and I/O PLLs 1.18. Internal Embedded Memory 1.19. Variable Precision DSP Block 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
1.5. Intel® Stratix® 10 MX Family Plan x
1.5.1. Available Options
1.9. Intel® Stratix® 10 MX Transceivers x
1.9.1. PMA Features 1.9.2. PCS Features
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview

1.5. Intel® Stratix® 10 MX Family Plan

Table 3.   Intel® Stratix® 10 MX Family Plan—FPGA Core (part 1)

Intel® Stratix® 10 MX Device Name

Logic

Elements

(KLE)

eSRAM Blocks eSRAM Mbits

M20K Blocks

M20K Mbits

MLAB Counts

MLAB Mbits

18x19 Multipliers 1

HPS Quad Core
MX 1650 1679 2 94.5 6,162 120 14,230 9 6,652 —
MX 2100 2073 2 94.5 6,847 134 17,568 11 7,920 —
Table 4.   Intel® Stratix® 10 MX Family Plan—Interconnects, PLLs, Hard IP, and HBM2 (part 2)

Intel® Stratix® 10 MX Device Name

Interconnects PLLs Hard IP HBM2 Tile Layout
Maximum GPIOs Maximum XCVR fPLLs I/O PLLs PCIe Hard IP Blocks 100GbE MACs Bandwidth (GByte/s) Density (GB)
MX 1650 656 96 32 16 4 4 512 8 2
MX 1650 656 96 32 16 4 4 512 16 3
MX 1650 584 96 8 16 1 13 512 8 4
MX 2100 640 48 16 16 2 2 512 8 1
MX 2100 656 96 32 16 4 4 512 8 2
MX 2100 656 96 32 16 4 4 512 16 3
MX 2100 584 96 8 16 1 13 512 8 4

Table 5.   Intel® Stratix® 10 MX Package Plan Cell legend: General Purpose I/Os, High-Voltage I/Os, LVDS Pairs, Transceivers, HBM2 Density Gbytes, HBM2 Bandwidth Gbytes/s, tile layout 2 3 4 5 6

Stratix 10 MX Device Name

F1760

NF43

(42.5x42.5 mm2)

F2597

NF53/UF53

(52.5x52.5 mm2)

F2912

UF55

(55x55 mm2)

MX 2100 N/A

640, 16, 312, 48

8, 512, tile layout 1

N/A
MX 1650 N/A

656, 32, 312, 96

8, 512, tile layout 2

584, 8, 288, 96

8, 512, tile layout 4

MX 2100 N/A

656, 32, 312, 96

8, 512, tile layout 2

584, 8, 288, 96

8, 512, tile layout 4

MX 1650 N/A

656, 32, 312, 96

16, 512, tile layout 3

N/A
MX 2100 N/A

656, 32, 312, 96

16, 512, tile layout 3

N/A
Figure 2. Tile Layout 1: Intel® Stratix® 10 MX Device with 2 H-Tiles (48 Transceiver Channels) and Two 4 GByte HBM2
Figure 3. Tile Layout 2: Intel® Stratix® 10 MX Device with 4 H-Tiles (96 Transceiver Channels) and Two 4 GByte HBM2
Figure 4. Tile Layout 3: Intel® Stratix® 10 MX Device with 4 H-Tiles (96 Transceiver Channels) and Two 8 GByte HBM2
Figure 5. Tile Layout 4: Intel® Stratix® 10 MX Device with 3 E-Tiles, 1 H-Tile (96 Transceiver Channels) and Two 4 GByte HBM2

Section Content
Available Options

1 The number of 27x27 multipliers is one-half the number of 18x19 multipliers.
2 All packages are ball grid arrays with 1.0 mm pitch.
3 High-Voltage I/O pins are used for 3 V and 2.5 V interfacing.
4 Each LVDS pair can be configured as either a differential input or a differential output.
5 High-Voltage I/O pins and LVDS pairs are included in the General Purpose I/O count. Transceivers are counted separately.
6 Each package column offers pin migration (common circuit board footprint) for all devices in the column.
Level Two Title