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1.1. Intel® Stratix® 10 MX Devices
1.2. Innovations in Intel® Stratix® 10 MX Devices
1.3. Intel® Stratix® 10 MX Features Summary
1.4. Intel® Stratix® 10 MX Block Diagram
1.5. Intel® Stratix® 10 MX Family Plan
1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory
1.7. Intel® Hyperflex™ Core Architecture
1.8. Heterogeneous 3D SiP Transceiver Tiles
1.9. Intel® Stratix® 10 MX Transceivers
1.10. PCI Express Gen1/Gen2/Gen3 Hard IP
1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP
1.12. 10G Ethernet Hard IP
1.13. Interlaken PCS Hard IP
1.14. External Memory and General Purpose I/O
1.15. Adaptive Logic Module (ALM)
1.16. Core Clocking
1.17. Fractional Synthesis PLLs and I/O PLLs
1.18. Internal Embedded Memory
1.19. Variable Precision DSP Block
1.20. Power Management
1.21. Device Configuration and Secure Device Manager (SDM)
1.22. Device Security
1.23. Configuration via Protocol Using PCI Express*
1.24. Partial and Dynamic Reconfiguration
1.25. Fast Forward Compile
1.26. Single Event Upset (SEU) Error Detection and Correction
1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
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1.9. Intel® Stratix® 10 MX Transceivers
Intel® Stratix® 10 MX devices offer up to 96 total full-duplex transceiver channels. These channels provide continuous data rates from 125 Mbps to 57.8 Gbps PAM4 / 28.9 Gbps NRZ for chip-to-chip, chip-to-module, and backplane applications. For longer-reach backplane driving applications, advanced adaptive equalization circuits are used to equalize over 30 dB of system loss.
All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a hardened Physical Coding Sublayer (PCS).
- The PMA provides primary interfacing capabilities to physical channels.
- The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.
Within each transceiver tile, the transceivers are arranged in four banks of six PMA-PCS groups. A wide variety of bonded and non-bonded data rate configurations are possible within each bank, and within each tile, using a highly configurable clock distribution network.