External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

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ID 683162
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives 5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Generating the Synthesizable EMIF Design Example 2.4. Generating the EMIF Design Example for Simulation 2.5. Simulation Versus Hardware Implementation 2.6. Simulating External Memory Interface IP With ModelSim 2.7. Pin Placement for Intel® Agilex™ 7 F-Series and I-Series EMIF IP 2.8. Compiling and Programming the Intel® Agilex™ 7 F-Series and I-Series EMIF Design Example 2.9. Generating a Design Example with the Calibration Debug Option 2.10. Generating a Design Example with the TG Configuration Option 2.11. Using the Design Example with the EMIF Debug Toolkit
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel® Agilex™ 7 F-Series and I-Series EMIF Parameter Editor Guidelines
2.10. Generating a Design Example with the TG Configuration Option x
2.10.1. Enabling the Traffic Generator in a Design Example
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Designs Interface Tab
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives
5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

2.8. Compiling and Programming the Intel® Agilex™ 7 F-Series and I-Series EMIF Design Example

After you have made the necessary pin assignments in the .qsf file, you can compile the design example in the Intel® Quartus® Prime software.

  1. Navigate to the Intel® Quartus® Prime folder containing the design example directory.
  2. Open the Intel® Quartus® Prime project file, (.qpf).
  3. To begin compilation, click Processing > Start Compilation. The successful completion of compilation generates a .sof file, which enables the design to run on hardware.
  4. To program your device with the compiled design, open the programmer by clicking Tools > Programmer.
  5. In the programmer, click Auto Detect to detect supported devices.
  6. Select the Intel® Agilex™ 7 device and then select Change File.
  7. Navigate to the generated ed_synth.sof file and select Open.
  8. Click Start to begin programming the Intel® Agilex™ 7 device. When the device is successfully programmed, the progress bar at the top-right of the window should indicate 100% (Successful).
Refer to Using the Design Example with the EMIF Debug Toolkit for guidance in debugging your external memory interface.
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