External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

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ID 683162
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP 4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives 5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Generating the Synthesizable EMIF Design Example 2.4. Generating the EMIF Design Example for Simulation 2.5. Simulation Versus Hardware Implementation 2.6. Simulating External Memory Interface IP With ModelSim 2.7. Pin Placement for Intel® Agilex™ 7 F-Series and I-Series EMIF IP 2.8. Compiling and Programming the Intel® Agilex™ 7 F-Series and I-Series EMIF Design Example 2.9. Generating a Design Example with the Calibration Debug Option 2.10. Generating a Design Example with the TG Configuration Option 2.11. Using the Design Example with the EMIF Debug Toolkit
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel® Agilex™ 7 F-Series and I-Series EMIF Parameter Editor Guidelines
2.10. Generating a Design Example with the TG Configuration Option x
2.10.1. Enabling the Traffic Generator in a Design Example
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Designs Interface Tab
1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives
5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide

2.7. Pin Placement for Intel® Agilex™ 7 F-Series and I-Series EMIF IP

This topic provides guidelines for pin placement.

Overview

Intel® Agilex™ 7 F-Series and I-Series FPGAs have the following structure:
  • Each device contains up to 8 I/O banks.
  • Each I/O bank contains 2 sub-I/O banks.
  • Each sub-I/O bank contains 4 lanes.
  • Each lane contains 12 general-purpose I/O (GPIO) pins.

General Pin Guidelines

The following are general pin guidelines.

Note: For more detailed pin information, refer to the Intel® Agilex™ 7 FPGA EMIF IP Pin and Resource Planning section in the protocol-specific chapter for your external memory protocol, in the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP User Guide.
  • Ensure that the pins for a given external memory interface reside within the same I/O row.
  • Interfaces that span multiple banks must meet the following requirements:
    • The banks must be adjacent to one another. For information on adjacent banks, refer to the EMIF Architecture: I/O Bank topic in the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP User Guide.
  • All address and command and associated pins must reside within a single sub-bank.
  • Address and command and data pins can share a sub-bank under the following conditions:
    • Address and command and data pins cannot share an I/O lane.
    • Only an unused I/O lane in the address and command bank can contain data pins.
Table 4.  General Pin Constraints
Signal Type Constraint
Data Strobe All signals belonging to a DQ group must reside in the same I/O lane.
Data Related DQ pins must reside in the same I/O lane. For protocols that do not support bidirectional data lines, read signals should be grouped separately from write signals.
Address and Command Address and Command pins must reside in predefined locations within an I/O sub-bank.

Adjacent Banks

For banks to be considered adjacent, they must reside in the same I/O row. To determine if banks are adjacent, refer to the EMIF Architecture: I/O Bank topic in the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP User Guide.

Pin Assignments

To determine locations for all EMIF I/O pins you should refer to the pin table for your device. When referring to the pin table, the bank numbers, I/O bank indices, and pin names are provided. You can find the pin indices for address and command pins in the Intel® Agilex™ 7 EMIF Pin Table at the following location: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html.

You can perform pin assignments in a variety of ways. The recommended approach is to manually constrain some interface signals and let the Intel® Quartus® Prime Fitter handle the rest. This method consists of consulting the pin tables to find legal positions for some of the interface pins and assigning them through the .qsf file that is generated with the EMIF design example. For this method of I/O placement, you must constrain the following signals:

  • CK0
  • One DQS pin per group
  • PLL reference clock
  • RZQ

Based on the above constraints, the Intel® Quartus® Prime Fitter rotates pins within each lane as necessary.

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