Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GT FPGA Datasheet

Download PDF
ID 683214
Date 11/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. FPGA Factory Image 7. Board Management Controller A. References B. Document Revision History for Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GT FPGA Datasheet
2. Overview x
2.1. Intel® PAC with Intel® Arria® 10 GT FPGA Block Diagram 2.2. Overview of Product Features
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GT FPGA 2.2.2. Fortville Network Interface Controller 2.2.3. On-Board Memory 2.2.4. Interfaces and Dimensions 2.2.5. Software 2.2.6. Power 2.2.7. Board Management Controller (BMC) 2.2.8. Network Interface 2.2.9. Control and Support
2.2.9. Control and Support x
2.2.9.1. Parkvale Retimer 2.2.9.2. PCIe Overview 2.2.9.3. Board Management Controller Overview
5. Thermal Specifications x
5.1. Thermal Test Performance Results
7. Board Management Controller x
7.1. BMC Features
7.1. BMC Features x
7.1.1. BMC Voltage and Thermal Handling
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. FPGA Factory Image
7. Board Management Controller
A. References
B. Document Revision History for Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GT FPGA Datasheet

7.1.1. BMC Voltage and Thermal Handling

The BMC powers down the Intel® PAC with Intel® Arria® 10 GT FPGA and reboots the server if the power, temperature or voltage reaches a certain threshold. This response prevents damage to the server or Intel® PAC with Intel® Arria® 10 GT FPGA.

For threshold limits refer to the Device Peripheral Table section. This table shows the upper non-recoverable (UNR) value, which specifies the shutdown condition. The BMC will shut down power to the board under conditions that include the following:
  • Backplane Voltage is below 10.46V
  • FPGA junction temperature reaches 100°C
Note:

The backplane power limits shown above are sufficient to protect the Intel® PAC with Intel® Arria® 10 GT FPGA hardware. If your server components require more conservative limits, you can change any threshold using PLDM commands as described in PLDM Commands for the Board Management Controller.

To avoid unintended shutdown and loss of data:

  • Use an Intel® -validated server.
  • Perform extensive power validation and consumption analysis on worst-case workloads.
  • Use a qualified solution that is stress-tested across multiple servers and long durations.

You can identify whether the BMC has detected a board failure from the two on-board LEDs. Looking into the bracket of the Intel® PAC through the venting holes on the back side of the server, you can see four steadily ON green LEDs. Behind them (further into the board), there is either a green LED or red LED that is on. The green LED blinks whenever the BMC is operating and is steadily on if the BMC is being initialized. When the BMC detects a failure condition and holds off board power, a red LED (next to the green LED) will be steadily on. Board failure conditions may occur because of an overheated FPGA or too much power draw from the board.

Related Information
Level Two Title