Stratix® 10 DX Device Overview

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ID 683225
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 DX Device Overview
1. Intel® Stratix® 10 DX Device Overview x
1.1. Intel® Stratix® 10 DX Devices 1.2. Intel® Stratix® 10 DX Features Summary 1.3. Intel® Stratix® 10 DX Block Diagram 1.4. Intel® Stratix® 10 DX Family Plan 1.5. Intel® Hyperflex™ Core Architecture 1.6. Heterogeneous 3D SiP Transceiver Tiles 1.7. Intel® Stratix® 10 DX Transceivers 1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.9. External Memory and General Purpose I/O 1.10. Adaptive Logic Module (ALM) 1.11. Core Clocking 1.12. I/O PLLs 1.13. Internal Embedded Memory 1.14. Variable Precision DSP Block 1.15. Hard Processor System (HPS) 1.16. Power Management 1.17. Device Configuration and Secure Device Manager (SDM) 1.18. Device Security 1.19. Configuration via Protocol Using PCI Express* 1.20. Partial and Dynamic Reconfiguration 1.21. Fast Forward Compile 1.22. Single Event Upset (SEU) Error Detection and Correction 1.23. Document Revision History for the Intel® Stratix® 10 DX Device Overview
1.4. Intel® Stratix® 10 DX Family Plan x
1.4.1. Available Options
1.7. Intel® Stratix® 10 DX Transceivers x
1.7.1. Intel® P-Tile Transceivers and Hard IP 1.7.2. Intel® E-Tile Transceivers and Hard IP
1.15. Hard Processor System (HPS) x
1.15.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 DX Device Overview

1.7.2. Intel® E-Tile Transceivers and Hard IP

Intel® Stratix® 10 DX devices contain one E-tile.

Each E-tile contains up to 24 full-duplex dual-mode transceivers, each transceiver capable of supporting both Pulse Amplitude Modulation with 4 levels (PAM4) up to 57.8 Gbps, and non-return-to-zero (NRZ) up to 28.9 Gbps. In addition to the transceivers, each E-tile contains multiple instances of 10/25/100 Gbps Ethernet MAC + FEC hard IP blocks. Both Reed-Solomon and KP FEC hard IP blocks are included, allowing complete Ethernet interfaces to be implemented, simplifying the design of complex multi-port Ethernet systems.

Table 8.  Available E-Tile Transceiver Channels in Intel® Stratix® 10 DX FPGA Devices
Intel® Stratix® 10 DX Device Name Number of E-Tile Transceiver Channels Available E-Tile Transceiver Channel Locations
DX 1100 16 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15, 20, 21, 22, 23
DX 2100 24 0 through 23
DX 2800 8 0, 1, 2, 3, 12, 13, 14, 15

For more information about the E-tile transceivers and the E-tile Ethernet hard IP, refer to the Intel® Stratix® 10 E-Tile Transceiver PHY User Guide.

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