Stratix® 10 DX Device Overview

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ID 683225
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 DX Device Overview
1. Intel® Stratix® 10 DX Device Overview x
1.1. Intel® Stratix® 10 DX Devices 1.2. Intel® Stratix® 10 DX Features Summary 1.3. Intel® Stratix® 10 DX Block Diagram 1.4. Intel® Stratix® 10 DX Family Plan 1.5. Intel® Hyperflex™ Core Architecture 1.6. Heterogeneous 3D SiP Transceiver Tiles 1.7. Intel® Stratix® 10 DX Transceivers 1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.9. External Memory and General Purpose I/O 1.10. Adaptive Logic Module (ALM) 1.11. Core Clocking 1.12. I/O PLLs 1.13. Internal Embedded Memory 1.14. Variable Precision DSP Block 1.15. Hard Processor System (HPS) 1.16. Power Management 1.17. Device Configuration and Secure Device Manager (SDM) 1.18. Device Security 1.19. Configuration via Protocol Using PCI Express* 1.20. Partial and Dynamic Reconfiguration 1.21. Fast Forward Compile 1.22. Single Event Upset (SEU) Error Detection and Correction 1.23. Document Revision History for the Intel® Stratix® 10 DX Device Overview
1.4. Intel® Stratix® 10 DX Family Plan x
1.4.1. Available Options
1.7. Intel® Stratix® 10 DX Transceivers x
1.7.1. Intel® P-Tile Transceivers and Hard IP 1.7.2. Intel® E-Tile Transceivers and Hard IP
1.15. Hard Processor System (HPS) x
1.15.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 DX Device Overview

1.7.1. Intel® P-Tile Transceivers and Hard IP

Intel® Stratix® 10 DX devices contain one or more P-tiles, each P-tile containing up to 20 full-duplex transceiver channels, along with PCIe* Gen4 x16 hard IP and Intel® UPI hard IP. If all 20 channels from the P-tile are available in the device, the P-tile can be configured to support either a PCIe* interface or an Intel® UPI interface. If only 16 channels are available, the P-tile supports PCIe* but does not support Intel® UPI which requires all 20 channels. Support for protocols other than PCIe* or Intel® UPI is not possible with the P-tile; it is not possible to bypass the hard IP blocks and connect the P-tile transceivers directly to the FPGA fabric.

Table 6.   Intel® Stratix® 10 P-Tile PCIe* Features

Feature

Capability

PCIe* Configurations

  • Gen4 or Gen3, x16 endpoint or root port
  • Gen4 or Gen3, x8 + x8 static port bifurcation, endpoints only
  • Gen4 or Gen3, x4 + x4 + x4 + x4 static port bifurcation, root ports only
  • Gen2 and Gen1 configurations supported indirectly through link negotiation
  • x1, x2 widths supported indirectly through protocol width reduction capability
  • Chip-to-chip and low-loss cable support

Virtualization Support
  • Single-Root I/O Virtualization (SR-IOV), 8 physical functions (PF) and 2048 virtual functions (VF) per endpoint
  • Intel® Scalable IOV support for software-based virtualization
  • Virtual I/O Device (VIRTIO)

Switch Support
  • Transaction Layer Bypass (TLP bypass) enables PCIe* switch implementations using SWUP and SWDN ports
Table 7.   Intel® Stratix® 10 P-Tile Intel® UPI Features

Feature

Capability

Intel® UPI Configurations

  • 20 lane support for 9.6 GT/s, 10.4 GT/s, 11.2 GT/s data rates
  • PHY and Link Layer support for Home Agent soft IP, Home Agent is implemented in the FPGA fabric
  • Chip-to-chip and low-loss cable support
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