Cyclone® V Intel® FPGA IP for PCI Express* IP Core Release Notes

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ID 683239
Date 7/31/2023
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V Hard IP for PCI Express IP Core Release Notes
1. Cyclone V Hard IP for PCI Express IP Core Release Notes x
1.1. Cyclone V Hard IP for PCI Express IP Core v23.1 1.2. Cyclone V Hard IP for PCI Express IP Core v16.1 1.3. Cyclone V Hard IP for PCI Express IP Core v16.0 1.4. Cyclone V Hard IP for PCI Express IP Core v15.0 1.5. Cyclone V Hard IP for PCI Express IP Core v14.1 1.6. Cyclone V Hard IP for PCI Express IP Core v14.0 1.7. Cyclone V Hard IP for PCI Express IP Core v13.0 SP1
1. Cyclone V Hard IP for PCI Express IP Core Release Notes

1.3. Cyclone V Hard IP for PCI Express IP Core v16.0

Table 3.  v16.0 May 2016
Description Impact
For the V-Series Avalon® Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core, rearchitected the Write DMA module for the 128-bit interface to the Application Layer. Provides higher throughput for external memories.
For the V-Series Avalon-MM DMA for PCI Express IP Core, the 256-bit interface to the Application Layer now supports a maximum transfer size of 64 kilobytes (KB). Large transfers require fewer descriptor table entries.
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