Cyclone® V Intel® FPGA IP for PCI Express* IP Core Release Notes

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ID 683239
Date 7/31/2023
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1. Cyclone V Hard IP for PCI Express IP Core Release Notes
1. Cyclone V Hard IP for PCI Express IP Core Release Notes x
1.1. Cyclone V Hard IP for PCI Express IP Core v23.1 1.2. Cyclone V Hard IP for PCI Express IP Core v16.1 1.3. Cyclone V Hard IP for PCI Express IP Core v16.0 1.4. Cyclone V Hard IP for PCI Express IP Core v15.0 1.5. Cyclone V Hard IP for PCI Express IP Core v14.1 1.6. Cyclone V Hard IP for PCI Express IP Core v14.0 1.7. Cyclone V Hard IP for PCI Express IP Core v13.0 SP1
1. Cyclone V Hard IP for PCI Express IP Core Release Notes

1.6. Cyclone V Hard IP for PCI Express IP Core v14.0

Table 6.  v14.0 June 2014
Description Impact
Upgraded the Avalon-ST version to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. -
Added support for new V-Series PCIe with Avalon-MM DMA Interface IP Core. -
Added the following features to the Cyclone V Avalon-MM Hard IP for PCI Express IP core:
  • Added access to selected Configuration Space registers and link status registers through the optional Control Register Access (CRA) Avalon-MM slave port.
  • Added optional hard IP status bus that includes signals necessary to connect the Transceiver Reconfiguration Controller IP Core.
  • Added optional hard IP status extension bus which includes signals that are useful for debugging, including: link training, status, error, and Configuration Space signals.
All of these new features are optional. If you include either the hard IP status bus or status extension bus in you design, you must regenerate your design and connect the new bus.
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