3.1. Memory Block Types
Intel® provides various sizes of embedded memory blocks for various devices.
The parameter editor allows you to implement your memory in the following ways:
- Select the type of memory blocks available based on your target device. To select the appropriate memory block type for your device, obtain more information about the features of your selected embedded memory block in your target device, such as the maximum performance, supported configurations (depth × width), byte enable, power-up condition, and the write and read operation triggering.
- Use logic cells. As compared to embedded memory resources, using logic cells to create memory reduces the design performance and utilizes more area. This implementation is normally used when you have used up all the embedded memory resources. When logic cells are used, the parameter editor provides you with the following two types of logic cell implementations:
- Default logic cell style—the write operation triggers (internally) on the rising edge of the write clock and have continuous read. This implementation uses less logic cells and is faster, but it is not fully compatible with the Stratix® M512 emulation style.
- Stratix M512 emulation logic cell style—the write operation triggers (internally) on the falling edge of the write clock and performs read only on the rising edge of the read clock.
- Select the Auto option, which allows the software to automatically select the appropriate embedded memory resource. When you set the memory block type to Auto, the compiler favors larger block types that can support the memory capacity you require in a single embedded memory block. This setting gives the best performance and requires no logic elements (LEs) for glue logic. When you create the memory with specific embedded memory blocks, such as M9K, the compiler is still able to emulate wider and deeper memories than the block type supported natively. The compiler spans multiple embedded memory blocks (only of the same type) with glue logic added in the LEs as needed.
Note: To obtain proper implementation based on the memory configuration you set, allow the Intel® Quartus® Prime software to automatically choose the memory type. This gives the compiler the flexibility to place the memory function in any available memory resources based on the functionality and size.
| Device Family | Memory Block Type | |||||
|---|---|---|---|---|---|---|
| MLAB (640 bits) | M9K (9 Kbits) | M144K (144 Kbits) | M10K (10 Kbits) | M20K (20 Kbits) | Logic Cell (LC) | |
| Arria® II GX | Yes | Yes | – | – | – | Yes |
| Arria® II GZ | Yes | Yes | Yes | – | – | Yes |
| Arria® V | Yes | – | – | Yes | – | Yes |
| Intel® Arria® 10 | Yes | – | – | – | Yes | Yes |
| Cyclone® IV | – | Yes | – | – | – | Yes |
| Cyclone® V | Yes | – | – | Yes | – | Yes |
| Intel® Cyclone® 10 LP | – | Yes | – | – | – | Yes |
| Intel® Cyclone® 10 GX | Yes | – | – | – | Yes | Yes |
| MAX® II | – | – | – | – | – | Yes |
| Intel® MAX® 10 | – | Yes | – | – | – | Yes |
| Stratix® IV | Yes | Yes | Yes | – | – | Yes |
| Stratix® V | Yes | – | – | – | Yes | Yes |
Note: To identify the type of memory block that the software selects to create your memory, refer to the Fitter report after compilation.
1 MLAB blocks are not supported in simple dual-port RAM mode with mixed-width port feature, true dual-port RAM mode, and dual-port ROM mode.