AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

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ID 683262
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Platform Design Strategy for 56G PAM4 Channels 3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines
2. Platform Design Strategy for 56G PAM4 Channels x
2.1. Intel® Stratix® 10 E-Tile Transceiver Channel Usage Mode 2.2. Intel® Stratix® 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2) 2.3. PCB Design Flow
2.3. PCB Design Flow x
2.3.1. Design Target at 56 Gbps PAM4 Standard 2.3.2. PCB Materials and Stackup Design 2.3.3. FPGA PCB Design 2.3.4. PCB Pre-Layout Simulation Phase 2.3.5. PCB Post-Layout Simulation Phase
2.3.2. PCB Materials and Stackup Design x
2.3.2.1. Insertion Loss 2.3.2.2. Return Loss 2.3.2.3. Package Loss and Crosstalk 2.3.2.4. PCB Via Design 2.3.2.5. PCB Connector 2.3.2.6. Cable Usage in PCB Design
2.3.3. FPGA PCB Design x
2.3.3.1. FPGA PCB Breakout Design and Reference 2.3.3.2. P/N De-skew Strategy on Differential Pairs 2.3.3.3. Crosstalk - NEXT and FEXT in Differential Pairs
1. Introduction
2. Platform Design Strategy for 56G PAM4 Channels
3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

2.3.4. PCB Pre-Layout Simulation Phase

Pre-layout simulation is the preliminary phase of the PCB design. This link simulation models the channel on the PCB, and it must cover the items below:
  • Channel impedance corner sweep
  • Channel length/loss sweep
  • You may need to adjust the materials and stackup if the Channel Operating Margin (COM) simulation fails.
  • Record the optimized TX EQ from the COM simulation.

COM (Channel Operating Margin - IEEE802.3cd/bs)

COM is initially published in IEEE802.3cd.

  • Normative channel compliance is through COM computation with specified margin.
  • IEEE802.3cd/bs spec and COM are not fully finalized yet as of this document's publish date.
  • IEEE802.3cd/bs compliance check for the channels is mandatory. It is a fast way to check the compliance of the channels with scattering parameters or S-parameters in touchstone format.
  • The optimized TX FFE c(-2), c(-1), and c(1) may be used to assist in the IBIS-AMI simulation as a “starting point” for TX EQ settings based on the conversion table to be made available in the E-Tile IBIS-AMI model user guide (if the E-tile TX FIR starting point table or RX equalization alone cannot achieve the desired BER target).
  • COM tool is available in the Intel Advanced Link Analyzer (formerly JNEye) for you to test your channels.
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