Viterbi IP Core User Guide

Download PDF
ID 683280
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the Viterbi IP Core 2. Viterbi IP Core Getting Started 3. Viterbi IP Core Functional Description A. Viterbi IP Core User Guide Document Archives 4. Document Revision History
1. About the Viterbi IP Core x
1.1. Intel® DSP IP Core Features 1.2. Viterbi IP Core Features 1.3. DSP IP Core Device Family Support 1.4. DSP IP Core Verification 1.5. Viterbi IP Core Release Information 1.6. Viterbi IP Core Performance and Resource Utilization
2. Viterbi IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Viterbi IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. Viterbi IP Core Functional Description x
3.1. Decoder 3.2. Convolutional Encoder 3.3. Trellis Coded Modulation 3.4. Viterbi IP Core Parameters 3.5. Viterbi IP Core Interfaces and Signals
3.3. Trellis Coded Modulation x
3.3.1. Half-Rate Convolutional Codes 3.3.2. Trellis Decoder 3.3.3. About Converting Received Signals 3.3.4. Trellis Termination 3.3.5. Trellis Initialization
3.4. Viterbi IP Core Parameters x
3.4.1. Architecture 3.4.2. Code Sets 3.4.3. Viterbi Parameters 3.4.4. Test Data
3.4.1. Architecture x
3.4.1.1. BER Estimator 3.4.1.2. Node Synchronization
3.4.3. Viterbi Parameters x
3.4.3.1. Soft Symbol Input 3.4.3.2. State Metrics 3.4.3.3. Throughput Calculator 3.4.3.4. Latency Calculator
3.4.4. Test Data x
3.4.4.1. External Puncturing
3.5. Viterbi IP Core Interfaces and Signals x
3.5.1. Avalon-ST Interfaces in DSP IP Cores 3.5.2. Global Signals 3.5.3. Avalon-ST Sink Signals 3.5.4. Avalon Source-ST Signals 3.5.5. Configuration Signals 3.5.6. Status Signals 3.5.7. Viterbi IP Core Timing Diagrams
1. About the Viterbi IP Core
2. Viterbi IP Core Getting Started
3. Viterbi IP Core Functional Description
A. Viterbi IP Core User Guide Document Archives
4. Document Revision History

3.3.3. About Converting Received Signals

The Viterbi decoder calculates the distances to the nearest four symbol points as an unsigned number in the range 0...00 to 1...11 (number of softbits).
Where the range is equal to the radius of the symbol map. The decoder works with accumulative metrics (not Euclidean metrics), so the decoder inverts these distances (000 becomes 111; 001 becomes110).
Figure 12. Conversion of Received Symbol into Four Branch Metrics and a Sector Number

For example, consider a received symbol that lands in sector number 2 with the following distances to the four nearest symbol map points:

  • 1111
  • 1101
  • 1011
  • 0001

Where the distance of the radius for 4 softbits is 1111. The distances are inverted to obtain the following branch metrics:

  • Branch metric 0 = 0000
  • Branch metric 1 = 0010
  • Branch metric 2 = 0100
  • Branch metric 3 = 1110

The decoder uses the coded bits (c1, c0) to select the branch metric number, which it uses to decide where to connect the branch metrics to the rr input of the Viterbi decoder. Branch metric 3 goes to the most significant bits (MSB) of rr; branch metric 0 goes to the least significant bits (LSB) of rr.

Level Two Title