Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. AXI-Stream Broadcaster Intel® FPGA IP x
10.1. About the AXI-Stream Broadcaster IP 10.2. AXI-Stream Broadcaster IP Parameters 10.3. AXI-Stream Broadcaster IP Interfaces
10.1. About the AXI-Stream Broadcaster IP x
10.1.1. AXI-Stream Broadcaster IP Features 10.1.2. AXI-Stream Broadcaster IP Performance and Resources
11. Bits per Color Sample Adapter Intel FPGA IP x
11.1. About the Bits per Color Sample Adapter IP 11.2. Bits per Color Sample Adapter IP Parameters 11.3. Bits per Color Sample Adapter IP Interfaces 11.4. Bits per Color Sample Adapter IP Registers 11.5. Bits per Color Sample Adapter Software API
11.1. About the Bits per Color Sample Adapter IP x
11.1.1. Bits per Color Sample Adapter IP Performance and Resources
12. Black Level Correction Intel® FPGA IP x
12.1. About the Black Level Correction IP 12.2. Black Level Correction IP Parameters 12.3. Black Level Correction IP Functional Description 12.4. Black Level Correction IP Registers 12.5. Black Level Correction IP Software API
12.1. About the Black Level Correction IP x
12.1.1. Black Level Correction IP Performance and Resources
12.3. Black Level Correction IP Functional Description x
12.3.1. Black Level Correction IP Interfaces
13. Black Level Statistics Intel® FPGA IP x
13.1. About the Black Level Statistics IP 13.2. Black Level Statistics IP Parameters 13.3. Black Level Statistics IP Interfaces 13.4. Black Level Statistics IP Registers 13.5. Black Level Statistics IP Software API
13.1. About the Black Level Statistics IP x
13.1.1. Black Level Statistics IP Performance and Resources
14. Chroma Key Intel® FPGA IP x
14.1. About the Chroma Key IP 14.2. Chroma Key IP Parameters 14.3. Chroma Key IP Interfaces 14.4. Chroma Key Replacement 14.5. Chroma Key IP Registers 14.6. Chroma Key IP Software API
14.1. About the Chroma Key IP x
14.1.1. Chroma Key IP Performance and Resources
15. Chroma Resampler Intel® FPGA IP x
15.1. About the Chroma Resampler IP 15.2. Chroma Resampler IP Parameters 15.3. Chroma Resampler IP Functional Description 15.4. Chroma Resampler IP Registers 15.5. Chroma Resampler IP Software API
15.1. About the Chroma Resampler IP x
15.1.1. Chroma Resampler Performance and Resources
15.3. Chroma Resampler IP Functional Description x
15.3.1. Chroma Resampler IP Interfaces
16. Clipper Intel® FPGA IP x
16.1. About the Clipper IP 16.2. Clipper IP Parameters 16.3. Clipper IP Interfaces 16.4. Clipper IP Registers 16.5. Clipper IP Software API
16.1. About the Clipper IP x
16.1.1. Clipper IP Performance and Resources
17. Clocked Video Input Intel® FPGA IP x
17.1. About the Clocked Video Input IP 17.2. Initializing the Clocked Video Input IP 17.3. Clocked Video Input IP Parameters 17.4. Clocked Video Input IP Interfaces 17.5. Clocked Video Input IP Registers 17.6. Clocked Video Input IP Software API
17.1. About the Clocked Video Input IP x
17.1.1. Clocked Video Input IP Features 17.1.2. Clocked Video Input IP Performance and Resources
18. Clocked Video to Full-Raster Converter Intel® FPGA IP x
18.1. About the Clocked Video to Full-Raster Converter IP 18.2. Clocked Video to Full-Raster Converter Parameters 18.3. Clocked Video to Full-Raster Converter Block Description 18.4. Clocked Video Converter to Full-Raster IP Registers
18.1. About the Clocked Video to Full-Raster Converter IP x
18.1.1. Clocked Video to Full-Raster Converter Features 18.1.2. Clocked Video to Full-Raster Converter Performance and Resources
18.3. Clocked Video to Full-Raster Converter Block Description x
18.3.1. Clocked Video to Full-Raster Converter Interfaces
19. Clocked Video Output Intel® FPGA IP x
19.1. About the Clocked Video Output IP 19.2. Clocked Video Output IP Parameters 19.3. Clocked Video Output IP Functional Description 19.4. Clocked Video Output IP Interfaces 19.5. Clocked Video Output IP Registers 19.6. Clocked Video Output IP Software API
19.1. About the Clocked Video Output IP x
19.1.1. Clocked Video Output IP Performance and Resources 19.1.2. Clocked Video Output IP Features
20. Color Plane Manager Intel® FPGA IP x
20.1. About the Color Plane Manager IP 20.2. Color Plane Manager IP Parameters 20.3. Color Plane Manager IP Functional Description 20.4. Color Plane Manager IP Registers 20.5. Color Plane Manager Software API
20.1. About the Color Plane Manager IP x
20.1.1. Color Plane Manager IP Performance and Resources
20.3. Color Plane Manager IP Functional Description x
20.3.1. Color Plane Manager IP Interfaces
21. Color Space Converter Intel® FPGA IP x
21.1. About the Color Space Converter IP 21.2. Color Space Converter IP Parameters 21.3. Color Space Converter IP Functional Description 21.4. Color Space Converter IP Registers 21.5. Color Space Converter IP Software API
21.1. About the Color Space Converter IP x
21.1.1. Color Space Converter IP Features 21.1.2. Color Space Converter IP Performance and Resources
21.3. Color Space Converter IP Functional Description x
21.3.1. Color Space Converter IP Interfaces
22. Defective Pixel Correction Intel® FPGA IP x
22.1. About the Defective Pixel Correction IP 22.2. Defective Pixel Correction IP Parameters 22.3. Defective Pixel Correction IP Functional Description 22.4. Defective Pixel Correction IP Registers 22.5. Defective Pixel Correction IP Software API
22.1. About the Defective Pixel Correction IP x
22.1.1. Defective Pixel Correction IP Performance and Resources
22.3. Defective Pixel Correction IP Functional Description x
22.3.1. Defective Pixel Correction IP Interfaces
23. Deinterlacer Intel® FPGA IP x
23.1. About the Deinterlacer IP 23.2. Deinterlacer Parameters 23.3. Deinterlacer Interfaces 23.4. Deinterlacer IP Registers 23.5. Deinterlacer IP Software API
23.1. About the Deinterlacer IP x
23.1.1. Deinterlacer Performance and Resources
24. Demosaic Intel® FPGA IP x
24.1. About the Demosaic IP 24.2. Demosaic IP Parameters 24.3. Demosaic IP Functional Description 24.4. Demosaic IP Registers 24.5. Demosaic IP Software API
24.1. About the Demosaic IP x
24.1.1. Demosaic IP Performance and Resources
24.3. Demosaic IP Functional Description x
24.3.1. Demosaic IP Interfaces
25. FIR Filter Intel® FPGA IP x
25.1. About the FIR Filter 25.2. FIR Filter Parameters 25.3. FIR Filter IP Operation 25.4. FIR Filter Interfaces 25.5. FIR Filter Registers 25.6. FIR Filter IP Software API
25.1. About the FIR Filter x
25.1.1. FIR Filter IP Performance and Resources
25.3. FIR Filter IP Operation x
25.3.1. FIR Filter Processing 25.3.2. FIR Filter Precision 25.3.3. FIR Coefficient Specification 25.3.4. FIR Filter Symmetry 25.3.5. Result to Output Data Type Conversion
25.3.4. FIR Filter Symmetry x
25.3.4.1. No Symmetry 25.3.4.2. Horizontal Symmetry 25.3.4.3. Vertical Symmetry 25.3.4.4. Horizontal and Vertical Symmetry 25.3.4.5. Diagonal Symmetry
26. Frame Cleaner Intel® FPGA IP x
26.1. About the Frame Cleaner IP 26.2. Frame Cleaner IP Parameters 26.3. Frame Cleaner IP Functional Description 26.4. Frame Cleaner IP Interfaces 26.5. Frame Cleaner IP Registers 26.6. Frame Cleaner IP Software API
26.1. About the Frame Cleaner IP x
26.1.1. Frame Cleaner IP Performance and Resources
27. Full-Raster to Clocked Video Converter Intel® FPGA IP x
27.1. About the Full-Raster to Clocked Video Converter 27.2. Full Raster to Clocked Video Converter Parameters 27.3. Full-Raster to Clocked Video Converter Block Description 27.4. Full-Raster to Clocked Video Converter Registers
27.1. About the Full-Raster to Clocked Video Converter x
27.1.1. Full-Raster to Clocked Video Converter Features 27.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
27.3. Full-Raster to Clocked Video Converter Block Description x
27.3.1. Full Raster to Clocked Video Converter Interfaces
28. Full-Raster to Streaming Converter Intel® FPGA IP x
28.1. About the Full-Raster to Streaming Converter IP 28.2. Full-Raster to Streaming Converter Parameters 28.3. Full-Raster to Streaming Converter Block Description
28.1. About the Full-Raster to Streaming Converter IP x
28.1.1. Full-Raster to Streaming Converter Features 28.1.2. Full-Raster to Streaming Converter Performance and Resources
28.3. Full-Raster to Streaming Converter Block Description x
28.3.1. Full-Raster to Streaming Converter Interfaces
29. Genlock Controller Intel® FPGA IP x
29.1. About the Genlock Controller IP 29.2. Genlock Controller IP Parameters 29.3. Genlock Controller IP Functional Description 29.4. Using Genlock Controller IP Software 29.5. Genlock Controller IP Registers 29.6. Genlock Controller IP Software API
29.1. About the Genlock Controller IP x
29.1.1. Genlock Controller IP Performance and Resources
29.3. Genlock Controller IP Functional Description x
29.3.1. Genlock Controller IP Interfaces
29.4. Using Genlock Controller IP Software x
29.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 29.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 29.4.3. Setting the VCXO hold over 29.4.4. Restarting the Genlock Controller IP 29.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 29.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 29.4.7. Disturbing a Reference Clock (a cable pull)
30. Generic Crosspoint Intel® FPGA IP x
30.1. About the Generic Crosspoint IP 30.2. Generic Crosspoint IP Parameters 30.3. Generic Crosspoint IP Interfaces 30.4. Generic Crosspoint IP Registers 30.5. Generic Crosspoint IP Software API
30.1. About the Generic Crosspoint IP x
30.1.1. Generic Crosspoint IP Features 30.1.2. Generic Crosspoint Performance and Resources
31. Genlock Signal Router Intel® FPGA IP x
31.1. About the Genlock Signal Router IP 31.2. Genlock Signal Router IP Parameters 31.3. Genlock Signal Router IP Interfaces 31.4. Genlock Signal Router IP Registers 31.5. Genlock Signal Router IP Software API
31.1. About the Genlock Signal Router IP x
31.1.1. Genlock Signal Router IP Features 31.1.2. Genlock Signal Router IP Performance and Resources
32. Guard Bands Intel® FPGA IP x
32.1. About the Guard Bands IP 32.2. Guard Bands IP Parameters 32.3. Guard Bands IP Interfaces 32.4. Guard Bands IP Registers 32.5. Guard Bands IP Software API
32.1. About the Guard Bands IP x
32.1.1. Guard Bands IP Performance and Resources
33. Histogram Statistics Intel® FPGA IP x
33.1. About the Histogram Statistics IP 33.2. Histogram Statistics IP Parameters 33.3. Histogram Statistics IP Interfaces 33.4. Histogram Statistics IP Registers 33.5. Histogram Statistics IP Software API
33.1. About the Histogram Statistics IP x
33.1.1. Histogram Statistics IP Performance and Resources
34. Interlacer Intel® FPGA IP x
34.1. About the Interlacer IP 34.2. Interlacer IP Parameters 34.3. Interlacer IP Functional Description 34.4. Interlacer IP Registers 34.5. Interlacer IP Software API
34.1. About the Interlacer IP x
34.1.1. Interlacer IP Performance and Resources
34.3. Interlacer IP Functional Description x
34.3.1. Interlacer IP Interfaces
35. Mixer Intel® FPGA IP x
35.1. About the Mixer IP 35.2. Mixer IP Parameters 35.3. Mixer IP Functional Description 35.4. Mixer IP Registers 35.5. Mixer IP Software API
35.1. About the Mixer IP x
35.1.1. Mixer IP Performance and Resources
35.3. Mixer IP Functional Description x
35.3.1. Mixer IP Interfaces
36. Pixels in Parallel Converter Intel® FPGA IP x
36.1. About the Pixels in Parallel Converter IP 36.2. Pixels in Parallel Converter IP Parameters 36.3. Pixels in Parallel Converter Interfaces 36.4. Pixels in Parallel Converter Registers 36.5. Pixels in Parallel Converter IP Software API
36.1. About the Pixels in Parallel Converter IP x
36.1.1. Pixels in Parallel Converter IP Performance and Resources
37. Scaler Intel® FPGA IP x
37.1. About the Scaler 37.2. Scaler IP Parameters 37.3. Scaler IP Functional Description 37.4. Scaler IP Registers 37.5. Scaler IP Software API
37.1. About the Scaler x
37.1.1. Scaler IP Performance and Resources
37.2. Scaler IP Parameters x
37.2.1. Scaler Maximum Resolution
37.3. Scaler IP Functional Description x
37.3.1. Coefficient Selection 37.3.2. Coefficient Quantization 37.3.3. Filter Behavior at Edge Boundaries 37.3.4. Partial Frame Scaling 37.3.5. 422 and 420 Chroma Sampled Data Scaling 37.3.6. Scaler IP Interfaces
37.3.1. Coefficient Selection x
37.3.1.1. Updating Scaler IP Runtime Coefficients
38. Stream Cleaner Intel® FPGA IP x
38.1. About the Stream Cleaner IP 38.2. Stream Cleaner IP Parameters 38.3. Stream Cleaner IP Functional Description
38.1. About the Stream Cleaner IP x
38.1.1. Stream Cleaner IP Performance and Resources
38.3. Stream Cleaner IP Functional Description x
38.3.1. Stream Cleaner IP Interfaces
39. Switch Intel® FPGA IP x
39.1. About the Switch IP 39.2. Switch IP Parameters 39.3. Switch IP Functional Description 39.4. Switch IP Registers 39.5. Switch IP Software API
39.1. About the Switch IP x
39.1.1. Switch IP Performance and Resources
39.3. Switch IP Functional Description x
39.3.1. Switch IP Latency 39.3.2. Switch IP Interfaces
40. Tone Mapping Operator Intel® FPGA IP x
40.1. About the Tone Mapping Operator IP 40.2. TMO IP Parameters 40.3. TMO IP Block Description 40.4. TMO IP Registers 40.5. TMO IP Software API
40.1. About the Tone Mapping Operator IP x
40.1.1. TMO IP Features 40.1.2. TMO IP Performance and Resource Utilization
40.3. TMO IP Block Description x
40.3.1. TMO IP Interfaces 40.3.2. TMO IP Latency
41. Test Pattern Generator Intel® FPGA IP x
41.1. About the Test Pattern Generator IP 41.2. Test Pattern Generator IP Parameters 41.3. Test Pattern Generator IP Functional Description 41.4. Test Pattern Generator IP Registers 41.5. Test Pattern Generator IP Software API
41.1. About the Test Pattern Generator IP x
41.1.1. Test Pattern Generator IP Performance and Resources
41.3. Test Pattern Generator IP Functional Description x
41.3.1. Test Pattern Generator IP Interfaces
42. Unsharp Mask Intel® FPGA IP x
42.1. About the Unsharp Mask IP 42.2. Unsharp Mask IP Parameters 42.3. Unsharp Mask IP Functional Description 42.4. Unsharp Mask IP Registers 42.5. Unsharp Mask IP Software API
42.1. About the Unsharp Mask IP x
42.1.1. Unsharp Mask IP Performance and Resources
42.3. Unsharp Mask IP Functional Description x
42.3.1. Unsharp Mask IP Interfaces
43. Video and Vision Monitor Intel FPGA IP x
43.1. About the Video and Vision Monitor IP 43.2. Video and Vision Monitor IP Parameters 43.3. Video and Vision Monitor IP Functional Description 43.4. Video and Vision Monitor IP Registers 43.5. Video and Vision Monitor Software API
43.1. About the Video and Vision Monitor IP x
43.1.1. Video and Vision Monitor IP Performance and Resources
43.3. Video and Vision Monitor IP Functional Description x
43.3.1. Video and Vision Monitor IP Interfaces
44. Video Frame Buffer Intel® FPGA IP x
44.1. About the Video Frame Buffer IP 44.2. Video Frame Buffer IP Parameters 44.3. Video Frame Buffer IP Functional Description 44.4. Video Frame Buffer IP Registers 44.5. Video Frame Buffer IP Software API
44.1. About the Video Frame Buffer IP x
44.1.1. Video Frame Buffer Performance and Resources
44.3. Video Frame Buffer IP Functional Description x
44.3.1. Video Frame Buffer IP Interfaces
45. Video Frame Reader Intel FPGA IP x
45.1. About the Video Frame Reader IP 45.2. Video Frame Reader IP Parameters 45.3. Video Frame Reader IP Functional Description 45.4. Video Frame Reader IP Registers 45.5. Video Frame Reader IP Software API
45.1. About the Video Frame Reader IP x
45.1.1. Video Frame Reader IP Performance and Resources
45.3. Video Frame Reader IP Functional Description x
45.3.1. Video Frame Reader IP Interfaces
46. Video Frame Writer Intel FPGA IP x
46.1. About the Video Buffer Writer IP 46.2. Video Frame Writer IP Parameters 46.3. Video Frame Writer IP Functional Description 46.4. Video Frame Writer IP Registers 46.5. Video Frame Writer IP Software API
46.1. About the Video Buffer Writer IP x
46.1.1. Video Frame Writer IP Performance and Resources
46.3. Video Frame Writer IP Functional Description x
46.3.1. Video Frame Writer IP Interfaces
47. Video Streaming FIFO Intel® FPGA IP x
47.1. About the Video Streaming FIFO IP 47.2. Video Streaming FIFO IP Parameters 47.3. Video Streaming FIFO IP Interfaces
47.1. About the Video Streaming FIFO IP x
47.1.1. Video Streaming FIFO IP Performance and Resources
48. Video Timing Generator Intel® FPGA IP x
48.1. About the Video Timing Generator IP 48.2. Video Timing Generator IP Parameters 48.3. Video Timing Generator IP Functional Description 48.4. Video Timing Generator IP Interfaces 48.5. Video Timing Generator IP Registers 48.6. Video Timing Generator IP Software API
48.1. About the Video Timing Generator IP x
48.1.1. Video Timing Generator IP Features 48.1.2. Video Timing Generator IP Performance and Resources
49. Vignette Correction Intel® FPGA IP x
49.1. About the Vignette Correction IP 49.2. Vignette Correction IP Parameters 49.3. Vignette Correction IP Interfaces 49.4. Vignette Correction IP Registers 49.5. Vignette Correction IP Software API
49.1. About the Vignette Correction IP x
49.1.1. Vignette Correction IP Performance and Resources
50. Warp Intel® FPGA IP x
50.1. About the Warp IP 50.2. Warp IP Parameters 50.3. Warp IP Block Description 50.4. Warp IP Registers 50.5. Warp IP Software API
50.1. About the Warp IP x
50.1.1. Warp IP Features 50.1.2. Warp IP Performance and Resource Utilization
50.3. Warp IP Block Description x
50.3.1. Block Cache Tool 50.3.2. Warp IP Interfaces 50.3.3. Warp IP Latency 50.3.4. External Memory for Warp IP
50.5. Warp IP Software API x
50.5.1. Using Warp IP Software 50.5.2. Warp IP Software Code Examples
51. White Balance Correction Intel® FPGA IP x
51.1. About the White Balance Correction IP 51.2. White Balance Correction IP Parameters 51.3. White Balance Correction IP Functional Description 51.4. White Balance Correction IP Registers 51.5. White Balance Correction IP Software API
51.1. About the White Balance Correction IP x
51.1.1. White Balance Correction IP Performance and Resources
51.3. White Balance Correction IP Functional Description x
51.3.1. White Balance Correction IP Interfaces
52. White Balance Statistics Intel® FPGA IP x
52.1. About the White Balance Statistics IP 52.2. White Balance Statistics IP Parameters 52.3. White Balance Statistics IP Interfaces 52.4. White Balance Statistics IP Registers 52.5. White Balance Statistics IP Software API
52.1. About the White Balance Statistics IP x
52.1.1. White Balance Statistics IP Performance and Resources
53. Design Security x
53.1. Memory Subsystems 53.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. AXI-Stream Broadcaster Intel® FPGA IP
11. Bits per Color Sample Adapter Intel FPGA IP
12. Black Level Correction Intel® FPGA IP
13. Black Level Statistics Intel® FPGA IP
14. Chroma Key Intel® FPGA IP
15. Chroma Resampler Intel® FPGA IP
16. Clipper Intel® FPGA IP
17. Clocked Video Input Intel® FPGA IP
18. Clocked Video to Full-Raster Converter Intel® FPGA IP
19. Clocked Video Output Intel® FPGA IP
20. Color Plane Manager Intel® FPGA IP
21. Color Space Converter Intel® FPGA IP
22. Defective Pixel Correction Intel® FPGA IP
23. Deinterlacer Intel® FPGA IP
24. Demosaic Intel® FPGA IP
25. FIR Filter Intel® FPGA IP
26. Frame Cleaner Intel® FPGA IP
27. Full-Raster to Clocked Video Converter Intel® FPGA IP
28. Full-Raster to Streaming Converter Intel® FPGA IP
29. Genlock Controller Intel® FPGA IP
30. Generic Crosspoint Intel® FPGA IP
31. Genlock Signal Router Intel® FPGA IP
32. Guard Bands Intel® FPGA IP
33. Histogram Statistics Intel® FPGA IP
34. Interlacer Intel® FPGA IP
35. Mixer Intel® FPGA IP
36. Pixels in Parallel Converter Intel® FPGA IP
37. Scaler Intel® FPGA IP
38. Stream Cleaner Intel® FPGA IP
39. Switch Intel® FPGA IP
40. Tone Mapping Operator Intel® FPGA IP
41. Test Pattern Generator Intel® FPGA IP
42. Unsharp Mask Intel® FPGA IP
43. Video and Vision Monitor Intel FPGA IP
44. Video Frame Buffer Intel® FPGA IP
45. Video Frame Reader Intel FPGA IP
46. Video Frame Writer Intel FPGA IP
47. Video Streaming FIFO Intel® FPGA IP
48. Video Timing Generator Intel® FPGA IP
49. Vignette Correction Intel® FPGA IP
50. Warp Intel® FPGA IP
51. White Balance Correction Intel® FPGA IP
52. White Balance Statistics Intel® FPGA IP
53. Design Security
54. Document Revision History for Video and Vision Processing Suite User Guide

46.4. Video Frame Writer IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 873.   Video Frame Writer IP Registers

In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_VIDEO FRAME WRITER as appropriate and with an optional REG suffix.

Address Register Access Description
Parameterization registers
0x0000 VID_PID RO Read this register for the Video Frame Writer product ID. This register always returns 0x6AF7_0249.
0x0004 VERSION RO Read this register for the IP version information.
0x0008 LITE_MODE RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when Lite mode is off and 1 when on.

0x000C DEBUG_ENABLED RO Read this register to determine if Debug features is on.
0x0010 MAX_HEIGHT RO Read this register to determine the maximum supported frame height.
0x0014 MAX_WIDTH RO Read this register to determine the maximum supported frame width.
0x0018 BITS_PER_SYMBOL RO Read this register for the number of bits per symbol configured.
0x001C NUMBER_OF_COLOR_PLANES RO Read this register for the number of color planes.
0x0020 PIXELS_IN_PARALLEL RO Read this register for the number of pixels in parallel.
0x0024 PACKING RO Read this register for the pixel packing scheme.
0x0028 to 0x00FF RESERVED
Interrupt registers
0x0100 IRQ_CONTROL RW IRQ control. Set this register to configure interrupts
0x0104 IRQ_STATUS RW

Read this status register to see if an interrupt fired.

0x0108 to

0x011F

RESERVED

Control and Debug registers

0x0120 IMG_INFO_WIDTH RW / RO Image information width.
0x0124 IMG_INFO_HEIGHT RW / RO Image information height.
0x0128 IMG_INFO_INTERLACE RO

Image information interlace.

0x012C RESERVED RW / RO Reserved.
0x0130 IMG_INFO_COLORSPACE RW / RO Image information color space
0x0134 IMG_INFO_SUBSAMPLING RW / RO Image information subsampling.
0x0138 IMG_INFO_COSITING RW / RO Image information cositing.
0x013C IMG_INFO_FIELD_COUNT RW / RO Field count image information.
0x0140 STATUS RO Status register
0x0144 BUFFER_AVAILABLE RO Buffer available.
0x0148 BUFFER_WRITE_COUNT RO Buffer write count

This register is reset after a write to the COMMIT register.

0x014C BUFFER_START_ADDRESS RO

The start address of the buffer the IP most recently writes.

0x0150 BUFFER_F1_FLAG RO

Buffer F1 flag.
0x0154 BUFFER_FIELD_WIDTH RO Buffer field width,
0x0158 BUFFER_FIELD_HEIGHT RO Buffer field height.
0x015C RESERVED
0x0160 FIELD_COUNT RO The value from the end-of-field packet of the most recently written buffer.
0x0164 COMMIT RW

Write any value to the COMMIT register to commit new RW register values and request an update to the new settings.

0x0168 BUFFER_ACKNOWLEDGE RW

Write to the BUFFER_ACKNOWLEDGE register to reset the BUFFER_AVAILABLE register.

BUFFER_ACKNOWLEDGE is the one exception to the need to write to COMMIT after updating a RW register.

0x016C RUN RW

Set the required operating mode:

0 - Frame writer is not running (stopped)

1 - Frame writer is free-running

2 - Frame writer is not running (stopped)

3 - Frame writer is in single-shot mode.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field.

0x0170 NUM_BUFFERS RW

The number of buffers.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field.

0x0174 BUFFER_BASE RW

Buffer base address.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field

0x0178 INTER_BUFFER_OFFSET RW

Interbuffer address increment.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field

0x017C INTER_LINE_OFFSET RW

Interline address increment.

Any changes to this register must be followed by a write to the COMMIT register and take effect at the next start of field

0x0180 to 0x0193 RESERVED
0x0194

IRQ_LINE_THRESHOLD

RW

IRQ line threshold.

0x0198 OVERWRITE_BROKEN RW Set to overwrite broken fields..

Register Bit Descriptions

Table 874.  VID_PID
Name Bits Description
Frame writer version ID and product ID 31:0

This register always returns 0x6AF7_0249

  • 15:0 is the product ID and always returns 0x0249
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 875.  VERSION
Name Bits Description
Register map version 7:0 Register map version.
IP patch revision 15:8 -
IP update revision 23:16 Updated when the IP version changes.
IP major revision 31:24 Updated when the IP version changes.
Table 876.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on lite mode.
Unused 31:1 Unused.
Table 877.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 878.  MAX_HEIGHT
Name Bits Description
Max height 31:0 Returns the maximum supported frame height.
Table 879.  MAX_WIDTH
Name Bits Description
Max width 31:0 Returns the maximum supported frame width.
Table 880.  BITS_PER_SYMBOL
Name Bits Description
Bits per symbol 31:0 Returns the number of bits per symbol that the Intel Streaming Video output is configured for.
Table 881.  NUMBER_OF_COLOR_PLANES
Name Bits Description
Number of color planes 31:0 Returns the number of color planes that the Intel Streaming Video output is configured for.
Table 882.  PIXELS_IN_PARALLEL
Name Bits Description
Number of pixels in parallel 31:0 This register returns the number of pixels in parallel that the Intel Streaming Video output is configured for.
Table 883.  PACKING
Name Bits Description
Packing 31:0

This register returns the packing scheme that the IP uses:

0 = Perfect packing

1 = Color packing

2 = Pixel packing
Table 884.  IRQ_CONTROL
Name Bit Description
Field_write_irq 0

Set the field_write_irq bit of the IRQ_CONTROL register to enable interrupts on completing field writes. Clear to disable interrupts on completing field writes.

Line_write_irq 1

Set the line_write_irq bit of the IRQ_CONTROL register to enable interrupts on completion of line writes. Clear the line_write_irq bit to disable interrupts on completion of line writes.

Select which line generates the interrupt by programing IRQ_LINE_THRESHOLD with the required line number. Line numbers start from 0.

Table 885.  IRQ_STATUS
Name Bit Description
Field_write_irq 0

The IP sets the field_write_irq bit of the IRQ_STATUS register if the interrupt fires.

Write to the field_write_irq bit of the IRQ_STATUS register to clear down the interrupt.

line_write_irq 1 The IP sets the line_write_irq bit of the IRQ_STATUS register if the interrupt fires. Write to the line_write_irq bit of the IRQ_STATUS register to clear down the interrupt
Table 886.  IMG_INFO_WIDTH
Name Bits Description
width 16:0

The field width that the writer IP uses when writing to memory.

If Lite mode is on, this register is RW. Write the expected width in pixels of incoming fields.

If Lite mode is off, if debug features are on, this register is RO and contains the field width received via the image information packet.

The IP removes extra pixels from received fields wider than IMG_INFO_WIDTH. The IP writes narrower fields leaving pixels from any previous fields in the buffer unmodified.

After any changes to this register write to the COMMIT register, which takes effect at the next start of field.
Table 887.  IMG_INFO_HEIGHT
Name Bits Description
height 16:0

The field height that the writer uses when writing to memory.

If Lite mode is on, this register is RW. Write the expected height in lines of incoming fields.

If Lite mode is off, if debug features are on, this register is RO and contains the field height received via the image information packet.

The IP removes extra lines from fields received that are taller than IMG_INFO_HEIGHT.

Shorter fields leave pixels from any previous fields in the buffer unmodified.

After any changes to this register write to the COMMIT register, which takes effect at the next start of field.
Table 888.   IMG_INFO_INTERLACE
Name Bits Description
interlace 3:0

If Lite mode is on, the IP stores interlaced fields in the same way as progressive frames by the frame writer, so you do not need to set this nibble.

If Lite mode is off, if debug features are on, this register is RO and contains the interlaced nibble received via the image information packet.

Table 889.   IMG_INFO_COLORSPACE
Name Bits Description
colspace 6:0

Unused If Lite mode is on.

If Lite mode is off, if debug features are on, this register is RO and contains the colorspace received via the image information packet.

Table 890.  IMG_INFO_SUBSAMPLING
Name Bits Description
subsampling 1:0

Unused If Lite mode is on.

If Lite mode is off, if debug features are on, this register is RO and contains the subsampling received via the image information packet.

Table 891.  IMG_INFO_COSITING
Name Bits Description
co-siting 1:0

Unused If Lite mode is on.

If Lite mode is off, if debug features are on, this register is RO and contains the cositing received via the image information packet.

Table 892.  IMG_INFO_FIELD_COUNT
Name Bits Description
field_count 5:0

Unused If Lite mode is on.

If Lite mode is off, if debug features are on, this register is RO and contains the field_count received via the image information packet.

Table 893.  STATUS
Name Bit Description
Status 0 Read this register to determine the status of the frame writer. The IP sets the status bit if the write is currently writing a frame, and returns to 0 in between frames.
Pending run-time control 1 Read this register to determine if the IP has any pending register writes to commit. This bit goes high when a write occurs to one of the control registers and returns low at the end of the current frame after a write to the COMMIT register. If the frame writer is idle, this bit goes low directly after a write to the COMMIT register.
Table 894.   BUFFER_AVAILABLE
Name Bit Description
Buffer available 0

After you write a field, the IP sets this bit and sets the BUFFER_START_ADDRESS, BUFFER_FIELD_WIDTH, BUFFER_FIELD_HEIGHT and BUFFER_F1_FLAG registers.

Clear the BUFFER_AVAILABLE bit by writing to the BUFFER_ACKNOWLEDGE register. The IP does not update BUFFER_START_ADDRESS, BUFFER_FIELD_WIDTH, BUFFER_FIELD_HEIGHT and BUFFER_F1_FLAG registers until you clear BUFFER_AVAILABLE.

For a steady video input, software has the duration of one field (typically around 5-20 ms) to read the buffers and clear BUFFER_AVAILABLE before you lose any buffer information.

Table 895.  BUFFER_WRITE_COUNT
Name Bits Description
Write count 31:0

Increments with each buffer the IP writes and resets with a write to the COMMIT register.

If you set the OVERWRITE_BROKEN register, this counter does not increment for fields that the IP writes but subsequently overwrites.

Table 896.  BUFFER_START_ADDRESS
Name Bit Description
Start address 31:0

Provides the start address of the most recently written buffer.

The IP writes the first buffer to the address you specify with BUFFER_BASE.

Table 897.  BUFFER_F1_FLAG
Name Bit Description
F1 flag 0

If Lite mode is on, this bit provides the state of TUSER[1] for the most recently written buffer. The IP set this bit when it writes to interlaced F1 fields.

If Lite mode is off, the IP sets this to the binary AND of IntlaceNibble bits 3 and 2 from the image information packet.

Table 898.  BUFFER_FIELD_WIDTH
Name Bit Description
Field width 31:0

If Lite mode is on, the IP returns the current value in IMG_INFO_WIDTH.

If Lite mode is off, the IP sets these bits to the width in the image information packet.

Table 899.  BUFFER_FIELD_HEIGHT
Name Bit Description
Field height 31:0

If Lite mode is on, the IP returns the current value in IMG_INFO_HEIGHT.

If Lite mode is off, the IP sets these bits to the height in the image information packet.

Table 900.  FIELD_COUNT
Name Bit Description
Field count 15:0

If Lite mode is on this returns 0.

If Lite mode is off, the IP takes the value from the end of field packet of the most recently written buffer.

Table 901.  COMMIT
Name Bit Description
Commit 0

Write any value to the COMMIT register to commit new RW register values and request an update to the new settings.

The frame buffer updates to the new RW register settings at the next start of field.

The IP starts operating according to the new settings when you write the current. The IP lowers the pending_rtc bit in the status register at this time.

The BUFFER_ACKNOWLEDGE register is the only register that does not need to be followed by a write to commit.

Table 902.  BUFFER_ACKNOWLEDGE
Name Bit Description
Acknowledge 0

Write to the acknowledge bit to reset the BUFFER_AVAILABLE register.

You don't need to follow a write to the BUFFER_ACKNOWLEDGE register with a write to the COMMIT register for it to take effect.

Table 903.  RUN
Name Bits Description
Run 0

Set the run bit to start the IP writing fields.

Clear the run bit to stop the IP writing at the end of the current field.
Single shot 1

Set the single shot bit to configure single shot mode. The frame writer writes buffers until it reaches NUM_BUFFERS buffers and then switches to consume mode. The IP sets BUFFER_AVAILABLE register after the first field write completes. To perform another single-shot write, clear BUFFER_AVAILABLE by writing to BUFFER_ACKNOWLEDGE. BUFFER_AVAILABLE.

If this bit is clear, the IP operates in continuous free-running mode and after it reaches NUM_BUFFERS buffers, writing continues, starting at BUFFER_BASE again.

Use this mode with NUM_BUFFERS set to 1, or a small value.

After any changes to this register write to the COMMIT register, which take effect at the next start of field
Table 904.  NUM_BUFFERS
Name Bits Description
Num_buffers 23:0

The number of buffers. When all buffers are full, the frame writer wraps around and begins writing to BUFFER_BASE again unless you set the single shot bit of the RUN register is set.

After any changes to this register write to the COMMIT register, which take effect at the next start of field
Table 905.  BUFFER_BASE
Name Bit Description
Buffer_base 31:0 Frame writing resets to the buffer_base address whenever you commit a write to the RUN register.

After any changes to this register write to the COMMIT register, which take effect at the next start of field
Table 906.  INTER_BUFFER_OFFSET
Name Bits Description
Inter-buffer offset 31:0

Interbuffer address increment. To prevent fields overwriting one another in memory, you must set this so that the spacing between buffers is greater than the size of individual fields in memory.

Interbuffer offset must be word aligned

After any changes to this register write to the COMMIT register, which take effect at the next start of field
Table 907.  INTER_LINE_OFFSET
Name Bits Description
Inter-line offset 31:0

Interline address increment.

Usually set to the low byte of the next word address above

bytes per pixel * IMAGE_WIDTH.

To prevent lines overwriting one another in memory you must set this bit so it is equal or greater than the line width in memory.

Interline offset must be word aligned.

After any changes to this register write to the COMMIT register, which take effect at the next start of field
Table 908.  IRQ_LINE_THRESHOLD
Name Bit Description
IRQ line threshold 31:0 Set the IRQ line threshold in combination with setting bit 1 of IRQ_CONTROL for the IP to raise an interrupt every time it writes line number IRQ_LINE_THRESHOLD for a field.
Table 909.  OVERWRITE_BROKEN
Name Bit Description
overwrite_broken 0 If you set the overwrite_broken bit, the IP overwrites fields received where the broken bit is set in the EOF, or where the height does not match the expected height. Also the IP does not set the BUFFER_AVAILABLE bit and other buffer information registers for that field.
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