Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

Download PDF
ID 683358
Date 1/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. CvP Initialization in Intel® Cyclone® 10 GX 2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX 3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX 4. CvP Driver and Registers A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide
1. CvP Initialization in Intel® Cyclone® 10 GX x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Support for Intel® Cyclone® 10 GX Devices 1.4. CvP Initialization 1.5. CvP Compression and Encryption Features 1.6. CvP Pins
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX x
2.1. Designing CvP for an Open System 2.2. Designing CvP for a Closed System
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX x
3.1. Generating the Synthesis HDL Files for Intel® Cyclone® 10 GX PCI Express IP Core 3.2. Setting up the CvP Parameters in Device and Pin Options 3.3. Compiling the Design 3.4. Splitting the SOF File 3.5. Bringing up the Hardware
3.5. Bringing up the Hardware x
3.5.1. Installing Jungo WinDriver in Windows Systems 3.5.2. Installing Jungo WinDriver in Linux Systems 3.5.3. Modifying MSEL/DIP switch on Intel® Cyclone® 10 GX Dev-Kit 3.5.4. Programming CvP Images
4. CvP Driver and Registers x
4.1. CvP Driver Support 4.2. CvP Driver Flow 4.3. VSEC Registers for CvP
4.3. VSEC Registers for CvP x
4.3.1. Intel® -defined Vendor Specific Capability Header Register 4.3.2. Intel® -defined Vendor Specific Header Register 4.3.3. Intel® Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
1. CvP Initialization in Intel® Cyclone® 10 GX
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX
4. CvP Driver and Registers
A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

1.1. Benefits of Using CvP

The CvP configuration scheme has the following advantages:
  • Reduces system costs by reducing the size of the local flash device used to store the periphery configuration data.
  • Improves security for the proprietary core bitstream. CvP ensures that the PCIe host can exclusively access the FPGA core image.
  • Provides a simpler software model for configuration. A smart host can use the PCIe protocol and the application topology to initialize and update the FPGA fabric.
  • Facilitates adaptable hardware acceleration.
Level Two Title