Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

7.1.1.2. add_interface_port

Description

Adds a port to an interface on your module. The name must match the name of a signal on the top-level module in the HDL of your IP component. The port width and direction must be set before the end of the elaboration phase. You can set the port width as follows:
  • In the Main program, you can set the port width to a fixed value or a width expression.
  • If the port width is set to a fixed value in the Main program, you can update the width in the elaboration callback.

Availability

Main Program, Elaboration

Usage

add_interface_port <interface> <port> [<signal_type> <direction> <width_expression>]

Returns

Arguments

interface
The name of the interface to which this port belongs.
port
The name of the port. This name must match a signal in your top-level HDL for this IP component.
signal_type (optional)
The type of signal for this port, which must be unique. Refer to the Avalon Interface Specifications for the signal types available for each interface type.
direction (optional)
The direction of the signal. Refer to Direction Properties.
width_expression (optional)
The width of the port, in bits. The width may be a fixed value, or a simple arithmetic expression of parameter values.

Example

fixed width:
add_interface_port mm_slave s0_rdata readdata output 32

width expression:
add_parameter DATA_WIDTH INTEGER 32
add_interface_port s0 rdata readdata output "DATA_WIDTH/2"