Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

2.6.2. Adding the External PLL

The Interlaken (2nd Generation) IP core variations that target an L-Tile or H-Tile device require an external TX transceiver PLL to drive the TX transceiver clock, in order to compile and to function correctly in hardware. In many cases, the same PLL can be shared with other transceivers in your design.
You can create an external transceiver PLL from the IP Catalog:
  • Select the L-Tile/H-Tile Transceiver ATX PLL Intel® Stratix® 10 FPGA IP.
  • In the parameter editor, set the following parameter values:
    • Set PLL output frequency to one half the per-lane data rate of the IP core variation.
    • Set PLL auto mode reference clock frequency (integer) to the value you select for the transceiver reference clock frequency (pll_ref_clk) parameter in the Interlaken (2nd Generation) IP parameter editor.
    • Set VCCR_GXB and VCCT_GXB Supply Voltage for the transceiver to the same value you specify in the Interlaken (2nd Generation) IP parameter editor.

You must connect tx_serial_clock output from the ATX PLL to tx_serial_clk input of your Interlaken (2nd Generation) IP core.

For more information about ATX PLL connection and how to instantiate the ATX PLL, refer to the Instantiating the ATX PLL IP Core in the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.

To use fPLL as an external transceiver PLL, select L-Tile/H-Tile fPLL Intel® Stratix® 10 FPGA IP from the IP Catalog and set the parameters using the instructions in the Instantiating the fPLL IP Core in the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.

The Interlaken (2nd Generation) IP core variations that target an E-tile device contains transceiver PLLs and do not require an external PLL for the transceivers. These transceiver PLLs require a reference clock (pll_ref_clk). Refer to the E-Tile Transceiver PHY User Guide and Interlaken (2nd Generation) Design Example User Guide for the reference clock connections.

The E-tile PAM4 mode variations require an additional mac_clkin input clock generated by a PLL. This PLL must use the same reference clock source that drives the pll_ref_clk. Refer to Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations in Interlaken (2nd Generation) Intel FPGA IP Design Example User Guide for more information about mac_clkin connections.

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