Interlaken (2nd Generation) Intel® FPGA IP User Guide

Download PDF
ID 683396
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

1.3. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Intel® Quartus® Prime Pro Edition software. The number of ALMs and logic registers are rounded up to the nearest 100. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table: IP Supported Combinations of Number of Lanes and Data Rates.

Table 4.   Intel® Stratix® 10 FPGA Resource Utilization in Interlaken Mode for Multi-segment (Segment = 1)The following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 22.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Stratix® 10 L-tile 4 6.25 10078 22832 4293 28
12.5 10437 24406 4338 28
25.28 10673 24656 4694 28
25.78 10646 24890 4460 28
25.78125 10700 24766 4584 28
8 12.5 21394 50374 7189 52
10 12.5 27475 64674 7884 61
12 10.3125 22452 50374 8449 52
12.5 22475 50386 8437 52
Intel® Stratix® 10 H-tile 4 6.25 10093 22745 4380 28
12.5 10860 24928 4194 28
25.28 11047 25450 4280 28
25.78 11062 25475 4255 28
25.78125 11061 25333 4397 28
6 25.28 22063 50686 8154 52
25.78 21987 50085 8365 52
25.78125 21978 50013 8264 52
8 12.5 22231 51137 7185 52
25.28 22654 51891 7082 52
25.78 22634 51836 7054 52
25.78125 52205 52205 7181 52
10 12.5 27454 64706 7852 61
25.28 33738 80672 8717 100
25.78 33757 80658 8732 100
25.78125 33733 80251 8968 100
12 10.3125 23493 51756 8265 52
12.5 22452 51063 7760 52
25.28 36748 87366 10857 100
25.78 36778 87697 10381 100
25.78125 36744 87635 10523 100
Intel® Stratix® 10 E-tile (NRZ) 4 6.25 15864 33290 5877 28
12.5 15863 33259 5908 28
25.28 16096 33579 5949 28
25.78 16077 33665 5708 28
25.78125 16071 33562 5895 28
6 25.28 29562 62712 10685 52
25.78 29580 62381 10386 52
25.78125 29557 62003 10311 52
8 12.5 32348 68199 10329 52
25.28 32887 68468 10567 52
25.78 32849 68328 10560 52
25.78125 32829 68097 10491 52
10 12.5 41105 86332 12429 61
25.28 46555 100805 13445 100
25.78 46510 100989 12996 100
25.78125 46474 100981 13280 100
12 10.3125 49898 105170 13752 73
12.5 48088 102366 14567 85
25.28 51971 112538 15228 100
25.78 51983 112344 15407 100
25.78125 51952 112676 14630 100
Intel® Stratix® 10 E-tile (PAM4) 12 26.5625 64818 135955 20225 100
Table 5.   Intel® Stratix® 10 FPGA Resource Utilization in Interlaken Mode for Packet ModeThe following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 22.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Stratix® 10 L-tile 4 6.25 10093 22677 4452 28
12.5 10492 24451 4295 28
25.28 10729 24654 4402 28
25.78 10692 24939 4413 28
25.78125 10718 24882 4470 28
8 12.5 21502 50458 7107 52
10 12.5 27426 64464 8098 61
12 10.3125 22502 50691 8168 52
12.5 22454 50960 7899 52
Intel® Stratix® 10 H-tile 4 6.25 10097 22899 4230 28
12.5 10830 24970 4154 28
25.28 11081 25285 4447 28
25.78 11026 25324 4408 28
25.78125 11056 25404 4328 28
6 25.28 22087 50325 8016 52
25.78 21984 50211 7894 52
25.78125 22033 50107 8163 52
8 12.5 22173 51171 7153 52
25.28 22647 51255 7072 52
25.78 22676 51827 6971 52
25.78125 22572 51793 7051 52
10 12.5 27373 64426 8172 61
25.28 33767 80503 8793 100
25.78 33794 80468 8792 100
25.78125 33879 80630 8687 100
12 10.3125 23490 51767 8258 52
12.5 22442 50398 8429 52
25.28 36597 88240 10773 100
25.78 36652 87405 10611 100
25.78125 36751 87351 10667 100
Intel® Stratix® 10 E-tile (NRZ) 4 6.25 15895 33362 5812 28
12.5 15895 33402 5772 28
25.28 16113 33933 5851 28
25.78 16112 33609 5966 28
25.78125 16134 33705 5776 28
6 25.28 29611 62735 10322 52
25.78 29571 62594 10544 52
25.78125 29576 62110 10253 52
8 12.5 32395 67945 10584 52
25.28 32865 68728 10104 52
25.78 32903 68639 10278 52
25.78125 32857 68157 9907 52
10 12.5 41133 86836 11959 61
25.28 46577 101252 12909 100
25.78 46576 100558 13094 100
25.78125 46521 101228 12962 100
12 10.3125 50009 104712 14217 73
12.5 48091 102929 14013 85
25.28 52004 112561 14820 100
25.78 52048 112577 15425 100
25.78125 52041 112474 15281 100
Intel® Stratix® 10 E-tile (PAM4) 12 26.5625 64911 136481 19936 100
Table 6.   Intel® Agilex™ FPGA Resource Utilization in Interlaken Mode for Multi-segment (Segment = 1)The following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 22.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ E-tile (NRZ) 4 6.25 15289 30987 6896 28
12.5 15287 31207 6705 28
25.28 15505 31547 7129 28
25.78 15511 31416 7256 28
25.78125 15495 31417 7236 28
6 25.28 28477 59341 12960 52
25.78 28490 59883 12573 52
25.78125 28489 59635 12806 52
8 12.5 31303 63167 12965 52
25.28 31567 64296 13315 52
25.78 31532 64141 13350 52
25.78125 31555 64456 13203 52
10 12.5 39625 80335 15284 61
25.28 44632 94698 17127 100
25.78 44590 94892 16837 100
25.78125 44603 94600 17147 100
12 10.3125 48072 97979 17377 73
12.5 46187 95291 18063 85
25.28 49891 105243 20187 100
25.78 49906 105851 19511 100
25.78125 49882 105417 20049 100
Intel® Agilex™ E-tile (PAM4) 12 26.5625 63146 128087 24657 100
Table 7.   Intel® Agilex™ FPGA Resource Utilization in Interlaken Mode for Packet ModeThe following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 22.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ E-tile (NRZ) 4 6.25 15317 31064 6847 28
12.5 15324 31021 6813 28
25.28 15508 31554 7074 28
25.78 15509 31506 7098 28
25.78125 15507 31489 7141 28
6 25.28 28518 59307 12950 52
25.78 28500 59537 12831 52
25.78125 28468 59656 12695 52
8 12.5 31327 63552 12708 52
25.28 31571 64366 13295 52
25.78 31571 64367 13331 52
25.78125 31572 64341 13371 52
10 12.5 39600 80337 15184 61
25.28 44639 94532 17122 100
25.78 44621 94659 17087 100
25.78125 44768 94676 17130 100
12 10.3125 48153 97911 17567 73
12.5 46228 94989 18480 85
25.28 49948 105384 20020 100
25.78 49893 105548 19793 100
25.78125 50000 105468 20031 100
Intel® Agilex™ E-tile (PAM4) 12 26.5625 63179 128144 24614 100
Table 8.   Intel® Stratix® 10 E-tile Resource Utilization Numbers in Interlaken Look-aside ModeThe following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 22.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20 Blocks
Primary Secondary
Intel® Stratix® 10 E-tile ( NRZ) 4 6.25 10199 19004 3147 0
12.5 10233 18961 3202 0
25.28 10240 18701 3292 0
25.78 10267 18943 3220 0
25.78125 10253 18780 3097 0
6 25.28 15652 28139 4839 0
25.78 15609 28143 4634 0
25.78125 15630 28194 4631 0
8 12.5 21128 38794 6151 0
25.28 21313 38217 6269 0
25.78 21275 38281 6086 0
25.78125 21293 38316 6006 0
10 12.5 27094 50153 7707 0
25.28 27301 49339 7657 0
25.78 27319 49111 7832 0
25.78125 27307 49376 7688 0
12 10.3125 33526 61590 9307 0
12.5 33575 61789 9151 0
25.28 33542 61104 9073 0
25.78 33603 60757 9012 0
25.78125 33562 60867 8886 0
Intel® Stratix® 10 E-tile (PAM4) 12 26.5625 46639 83929 13336 0
Table 9.   Intel® Agilex™ E-tile Resource Utilization Numbers in Interlaken Look-aside ModeThe following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 22.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20 Blocks
Primary Secondary
Intel® Agilex™ E-tile (NRZ) 4 6.25 9727 17474 3829 0
12.5 9733 17494 3862 0
25.28 9736 17478 3956 0
25.78 9709 17519 4015 0
25.78125 9691 17434 4010 0
6 25.28 14789 26485 5891 0
25.78 14779 26505 5850 0
25.78125 14764 26174 6122 0
8 12.5 20188 35645 7692 0
25.28 23500 20137 35575 8011 0
25.78 23200 20139 35612 8012 0
25.78125 23400 20143 35619 8006 0
10 12.5 25762 45431 9702 0
25.28 25749 45395 10027 0
25.78 25761 45391 10047 0
25.78125 25774 45456 10059 0
12 10.3125 31773 55998 11612 0
12.5 31969 56214 11497 0
25.28 31897 56103 12003 0
25.78 31907 56088 12007 0
25.78125 31893 56071 11988 0
Intel® Agilex™ E-tile ( PAM4) 12 26.5625 44951 79209 16249 0
Related Information
Level Two Title