Cyclone® 10 GX Device Overview

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ID 683485
Date 4/01/2019
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Overview
Intel® Cyclone® 10 GX Device Overview x
Key Advantages of Intel® Cyclone® 10 GX Devices Summary of Intel® Cyclone® 10 GX Features Intel® Cyclone® 10 GX Available Options Intel® Cyclone® 10 GX Maximum Resources Intel® Cyclone® 10 GX Package Plan I/O Vertical Migration for Intel® Cyclone® 10 GX Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1 and Gen2 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Cyclone® 10 GX Device Overview
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Cyclone® 10 GX Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Cyclone® 10 GX Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Cyclone® 10 GX Device Overview

Document Revision History for Intel® Cyclone® 10 GX Device Overview

Document Version Changes
2019.04.01 Added support for partial reconfiguration.
2019.01.01 Updated I/O resource count for package F672 of the 10CX085 device.
2018.07.11 Removed mentions of Single Root I/O Virtualization (SR-IOV). The Intel® Cyclone® 10 GX devices do not support SR-IOV.
2018.05.07 Added footnote to the PCIe hard IP topic to list device and package combinations that support only x2 lane configuration.
Date Version Changes
November 2017 2017.11.06
  • The document is no longer preliminary.
  • Updated the 10 Gbps Ethernet Support section.
  • Updated the features supported in the PMA Features of the Transceivers in Intel® Cyclone® 10 GX Devices table.
  • Removed automotive support.
  • Removed the note about the migration paths in the I/O Vertical Migration for Intel® Cyclone® 10 GX Devices.
May 2017 2017.05.08 Initial release.
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