AN 893: Hierarchical Partial Reconfiguration Tutorial: for Intel Cyclone® 10 GX FPGA Development Board

ID 683548
Date 7/15/2019
Public

Reference Design Overview

This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 1. Flat Reference Design without PR Partitioning