Intel® Stratix® 10 DX FPGA Development Kit User Guide

Download PDF
ID 683561
Date 9/25/2023
Public
Document Table of Contents
Document Table of Contents x
1. Getting Started 2. Development Kit Overview 3. Power Up the Development Kit 4. Board Test System (BTS) 5. Development Kit Hardware and Configuration 6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide A. Development Kit Components B. Safety and Regulatory Information C. Compliance and Conformity Information
1. Getting Started x
1.1. About this Document 1.2. Installing the Intel® Quartus® Prime Pro Edition Software 1.3. Downloading the Board Package 1.4. Installing the Driver for Intel FPGA Download Cable II
1.2. Installing the Intel® Quartus® Prime Pro Edition Software x
1.2.1. Activating Your License
2. Development Kit Overview x
2.1. Supported Features 2.2. Recommended Operating Conditions 2.3. Handling the Board
3. Power Up the Development Kit x
3.1. Default Switch Settings 3.2. Connectors and LEDs 3.3. Performing Board Restore through Board Test System (BTS) 3.4. Controlling On-board Clock
4. Board Test System (BTS) x
4.1. Preparing the Development Kit 4.2. Running the Board Test System 4.3. Using the Board Test System 4.4. Smart VID Setting
4.3. Using the Board Test System x
4.3.1. Configure Menu 4.3.2. Sys Info Tab 4.3.3. GPIO Tab 4.3.4. QSFP Tab 4.3.5. Component DDR4 CH0 Tab 4.3.6. Component DDR4 CH1 Tab 4.3.7. DDR4 DIMM CH0 Tab 4.3.8. DDR4 DIMM CH1 Tab 4.3.9. Power Monitor 4.3.10. Clock Controller
5. Development Kit Hardware and Configuration x
5.1. FPGA Configuration 5.2. Programming the FPGA Over Intel® FPGA Download Cable 5.3. Configuration Modes
5.3. Configuration Modes x
5.3.1. Avalon® Streaming Interface x8 Mode 5.3.2. JTAG Mode
5.3.1. Avalon® Streaming Interface x8 Mode x
Avalon® Streaming Interface x8 Configuration Guideline
A. Development Kit Components x
A.1. Components Overview A.2. Power, Thermal, and Mechanical Considerations A.3. Clock Circuits A.4. Memory Interface A.5. PCIe Interface A.6. UPI Interface A.7. Transceiver Signals: PCIe and UPI Interface A.8. SlimSAS Connector A.9. QSFP Network Interface A.10. I2C Interface A.11. QSPI Flash Memory
A.2. Power, Thermal, and Mechanical Considerations x
A.2.1. Power Guidelines A.2.2. Thermal Requirements A.2.3. Mechanical Requirements
A.2.1. Power Guidelines x
A.2.1.1. Power Distribution A.2.1.2. Power Sequence A.2.1.3. Power Measurement
A.2.2. Thermal Requirements x
A.2.2.1. Operating Conditions A.2.2.2. Temperature Monitoring
A.9. QSFP Network Interface x
A.9.1. Dual Port Controller
A.11. QSPI Flash Memory x
A.11.1. Configuration QSPI Flash Memory A.11.2. NIOS QSPI Flash Memory
B. Safety and Regulatory Information x
B.1. Safety Warnings B.2. Safety Cautions
1. Getting Started
2. Development Kit Overview
3. Power Up the Development Kit
4. Board Test System (BTS)
5. Development Kit Hardware and Configuration
6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Information
C. Compliance and Conformity Information

3.1. Default Switch Settings

This development kit ships with its switches preconfigured to support the design examples in the kit. If you suspect that your board may not be correctly configured with the default settings, refer to the following table to return to its factory settings before proceeding.
Table 4.  Default Switch Settings
Switch Default Position Description
SW1[1:4] ON/OFF/OFF/X Configuration mode setting bits:
Mode MSEL0 MSEL1 MSEL2 QSPI_AVST_SEL
JTAG OFF (Open) OFF (Open) OFF (Open) X
Avalon-ST ON (Close) OFF (Open) OFF (Open) X
SW33[1:4] OFF/X/ON/ON JTAG, MAX10, UPI controls:
SW33 ON (Close) OFF (Open)
1 - JTAG Debug JTAG Header (J2) dedicated for Max10 Normal JTAG (Default)
2 - JTAG SOURCE Not used Not used
3 - UPI Mode 2 Sockets 4 Sockets
4 – M10 JTAG EN M10 JTAG Enabled M10 JTAG Disabled
SW2[1:4] ON/ON/ON/ON PCIe PRSNT X1/x4/x8/x16 settings:
PCIe PRSNT X1 PCIe PRSNT X4 PCIe PRSNT X8 PCIe PRSNT X16
ON (Close) ON (Close) ON (Close) ON (Close)
SW28 ON (Close) PCIe Edge connector PERSTn selection:
  • ON: Endpoint (Default)
  • OFF: Root Port
SW27 ON (Close) Intel® Stratix® 10 DX PERSTn selection:
  • ON: Endpoint (Default)
  • OFF: Root Port
SW16 ON (Close) UPI0 PERSTn selection:
  • ON: PERSTn from PCIe Edge connector to FPGA
  • OFF: PERSTn from FPFA to CPU (Default)
SW24 ON (Close) UPI0 PERSTn selection:
  • OFF: PERSTn from FPGA to CPU (Default)
  • ON: PERSTn from PCIe Edge connector to FPGA
SW17 ON (Close) UPI1 PERSTn selection:
  • ON: PERSTn from PCIe Edge connector to FPGA
  • OFF: PERSTn from FPFA to CPU (Default)
SW25 ON (Close) UPI1 PERSTn selection:
  • OFF: PERSTn from FPGA to CPU (Default)
  • ON: PERSTn from PCIe Edge connector to FPGA
SW18 ON (Close) UPI2 PERSTn selection:
  • ON: PERSTn from PCIe Edge connector to FPGA
  • OFF: PERSTn from FPFA to CPU (Default)
SW26 ON (Close) UPI2 PERSTn selection:
  • OFF: PERSTn from FPGA to CPU (Default)
  • ON: PERSTn from PCIe Edge connector to FPGA
SW14 ON (Close) PCIe REFCLK source selection:
  • ON: 100MHz REFCLK internal generated
  • OFF: 100MHz REFCLK from PCIe Edge Connector (Default)
SW31 ON (Close) or OFF (Open)
Power switch:
  • ON: Turn on power (set to this position for use in PCIe slot)
  • OFF: Turn off power
Note: This switch must be ON when the card is plugged into a PCIe slot (with 2x4 Aux power connected) or on the bench with external ATX power supply.
Figure 3. Location of Switches and Push Buttons
Table 5.  Push Buttons
Push Buttons Descriptions
S1 PCIe Reset Push to reset PCIe bus
S2 MAX10 Reset Push to reset Max10
S3 CPU Reset Push to reset FPGA
S4 USER Push Button Push button for user assigned function
Level Two Title