Intel® Quartus® Prime Standard Edition User Guide: PCB Design Tools

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ID 683619
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Simultaneous Switching Noise (SSN) Analysis and Optimizations 2. Signal Integrity Analysis with Third-Party Tools 3. Mentor Graphics* PCB Design Tools Support 4. Cadence PCB Design Tools Support 5. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software A. Intel® Quartus® Prime Standard Edition User Guides
1. Simultaneous Switching Noise (SSN) Analysis and Optimizations x
1.1. Simultaneous Switching Noise (SSN) Analysis and Optimizations 1.2. Definitions 1.3. Understanding SSN 1.4. SSN Estimation Tools 1.5. SSN Analysis Overview 1.6. Design Factors Affecting SSN Results 1.7. Optimizing Your Design for SSN Analysis 1.8. Performing SSN Analysis and Viewing Results 1.9. Decreasing Processing Time for SSN Analysis 1.10. Scripting Support 1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History
1.5. SSN Analysis Overview x
1.5.1. Performing Early Pin-Out SSN Analysis 1.5.2. Performing Final Pin-Out SSN Analysis
1.5.1. Performing Early Pin-Out SSN Analysis x
1.5.1.1. Performing Early Pin-Out SSN Analysis with the SSN Analyzer
1.7. Optimizing Your Design for SSN Analysis x
1.7.1. Optimizing Pin Placements for Signal Integrity 1.7.2. Specifying Board Trace Model Settings 1.7.3. Defining PCB Layers and PCB Layer Thickness 1.7.4. Specifying Signal Breakout Layers 1.7.5. Creating I/O Assignments 1.7.6. Decreasing Pessimism in SSN Analysis 1.7.7. Excluding Pins as Aggressor Signals
1.8. Performing SSN Analysis and Viewing Results x
1.8.1. Understanding the SSN Reports 1.8.2. Viewing SSN Analysis Results in the Pin Planner
1.8.1. Understanding the SSN Reports x
1.8.1.1. Summary Report 1.8.1.2. Output Pins Report and Input Pins Report 1.8.1.3. Unanalyzed Pins Report 1.8.1.4. Confidence Metric Details
1.10. Scripting Support x
1.10.1. Optimizing Pin Placements for Signal Integrity 1.10.2. Defining PCB Layers and PCB Layer Thickness 1.10.3. Specifying Signal Breakout Layers 1.10.4. Decreasing Pessimism in SSN Analysis 1.10.5. Performing SSN Analysis
2. Signal Integrity Analysis with Third-Party Tools x
2.1. Signal Integrity Analysis with Third-Party Tools 2.2. I/O Model Selection: IBIS or HSPICE 2.3. FPGA to Board Signal Integrity Analysis Flow 2.4. Simulation with IBIS Models 2.5. Simulation with HSPICE Models 1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History
2.1. Signal Integrity Analysis with Third-Party Tools x
2.1.1. Signal Integrity Simulations with HSPICE and IBIS Models
2.3. FPGA to Board Signal Integrity Analysis Flow x
2.3.1. Create I/O and Board Trace Model Assignments 2.3.2. Output File Generation 2.3.3. Customize the Output Files 2.3.4. Set Up and Run Simulations in Third-Party Tools 2.3.5. Interpret Simulation Results
2.4. Simulation with IBIS Models x
2.4.1. Elements of an IBIS Model 2.4.2. Creating Accurate IBIS Models 2.4.3. Design Simulation Using the Mentor Graphics* HyperLynx* Software 2.4.4. Configuring LineSim to Use Intel IBIS Models 2.4.5. Integrating Intel IBIS Models into LineSim Simulations 2.4.6. Running and Interpreting LineSim Simulations
2.4.2. Creating Accurate IBIS Models x
2.4.2.1. Download IBIS Models 2.4.2.2. Generate Custom IBIS Models with the IBIS Writer
2.5. Simulation with HSPICE Models x
2.5.1. Supported Devices and Signaling 2.5.2. Accessing HSPICE Simulation Kits 2.5.3. The Double Counting Problem in HSPICE Simulations 2.5.4. HSPICE Writer Tool Flow 2.5.5. Running an HSPICE Simulation 2.5.6. Interpreting the Results of an Output Simulation 2.5.7. Interpreting the Results of an Input Simulation 2.5.8. Viewing and Interpreting Tabular Simulation Results 2.5.9. Viewing Graphical Simulation Results 2.5.10. Making Design Adjustments Based on HSPICE Simulations 2.5.11. Sample Input for I/O HSPICE Simulation Deck 2.5.12. Sample Output for I/O HSPICE Simulation Deck 2.5.13. Advanced Topics
2.5.3. The Double Counting Problem in HSPICE Simulations x
2.5.3.1. Defining the Double Counting Problem 2.5.3.2. The Solution to Double Counting
2.5.4. HSPICE Writer Tool Flow x
2.5.4.1. Applying I/O Assignments 2.5.4.2. Enabling HSPICE Writer 2.5.4.3. Enabling HSPICE Writer Using Assignments 2.5.4.4. Naming Conventions for HSPICE Files 2.5.4.5. Invoking HSPICE Writer 2.5.4.6. Invoking HSPICE Writer from the Command Line 2.5.4.7. Customizing Automatically Generated HSPICE Decks
2.5.11. Sample Input for I/O HSPICE Simulation Deck x
2.5.11.1. Header Comment 2.5.11.2. Simulation Conditions 2.5.11.3. Simulation Options 2.5.11.4. Constant Definition 2.5.11.5. Buffer Netlist 2.5.11.6. Drive Strength 2.5.11.7. I/O Buffer Instantiation 2.5.11.8. Board Trace and Termination 2.5.11.9. Stimulus Model 2.5.11.10. Simulation Analysis
2.5.12. Sample Output for I/O HSPICE Simulation Deck x
2.5.12.1. Header Comment 2.5.12.2. Simulation Conditions 2.5.12.3. Simulation Options 2.5.12.4. Constant Definition 2.5.12.5. I/O Buffer Netlist 2.5.12.6. Drive Strength 2.5.12.7. Slew Rate and Delay Chain 2.5.12.8. I/O Buffer Instantiation 2.5.12.9. Board and Trace Termination 2.5.12.10. Double-Counting Compensation Circuitry 2.5.12.11. Simulation Analysis
2.5.13. Advanced Topics x
2.5.13.1. PVT Simulations 2.5.13.2. Hold Time Analysis 2.5.13.3. I/O Voltage Variations 2.5.13.4. Correlation Report
3. Mentor Graphics* PCB Design Tools Support x
3.1. FPGA-to-PCB Design Flow 3.2. Integrating with I/O Designer 3.3. Integrating with DxDesigner 3.4. Analyzing FPGA Simultaneous Switching Noise (SSN) 3.5. Scripting API 1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History
3.2. Integrating with I/O Designer x
3.2.1. Generating Pin Assignment Files 3.2.2. I/O Designer Settings 3.2.3. Transferring I/O Assignments 3.2.4. Updating I/O Designer with Intel® Quartus® Prime Pin Assignments 3.2.5. Updating Intel® Quartus® Prime with I/O Designer Pin Assignments 3.2.6. Generating Schematic Symbols in I/O Designer 3.2.7. Exporting Schematic Symbols to DxDesigner
3.2.6. Generating Schematic Symbols in I/O Designer x
3.2.6.1. Generating Schematic Symbols
3.3. Integrating with DxDesigner x
3.3.1. DxDesigner Project Settings 3.3.2. Creating Schematic Symbols in DxDesigner
4. Cadence PCB Design Tools Support x
4.1. Cadence PCB Design Tools Support 4.2. Product Comparison 4.3. FPGA-to-PCB Design Flow 4.4. Setting Up the Intel® Quartus® Prime Software 4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software 4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software 1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History
4.3. FPGA-to-PCB Design Flow x
4.3.1. Integrating Intel FPGA Design 4.3.2. Performing Simultaneous Switching Noise (SSN) Analysis of Your FPGA
4.4. Setting Up the Intel® Quartus® Prime Software x
4.4.1. Generating a .pin File
4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software x
4.5.1. Creating Symbols 4.5.2. Instantiating the Symbol in the Cadence Allegro Design Entry HDL Software
4.5.1. Creating Symbols x
4.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool
4.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool x
4.5.1.1.1. Cadence Allegro PCB Librarian Part Developer Tool in the Design Flow 4.5.1.1.2. Import and Export Wizard 4.5.1.1.3. Editing and Fracturing Symbol 4.5.1.1.4. Updating FPGA Symbols
4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software x
4.6.1. Creating a Cadence Allegro Design Entry CIS Project 4.6.2. Generating a Part 4.6.3. Generating Schematic Symbol 4.6.4. Splitting a Part 4.6.5. Instantiating a Symbol in a Design Entry CIS Schematic 4.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software
4.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software x
4.6.6.1. Using the Intel-provided Libraries with your Cadence Allegro Design Entry CIS Project
5. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software x
5.1. Reviewing Intel® Quartus® Prime Software Settings 5.2. Reviewing Device Pin-Out Information in the Fitter Report 5.3. Reviewing Compilation Error and Warning Messages 5.4. Using Additional Intel® Quartus® Prime Software Features 5.5. Using Additional Intel® Quartus® Prime Software Tools 1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History1.112.63.64.75.6. Document Revision History
5.1. Reviewing Intel® Quartus® Prime Software Settings x
5.1.1. Device and Pins Options Dialog Box Settings
5.1.1. Device and Pins Options Dialog Box Settings x
5.1.1.1. Configuration Settings 5.1.1.2. Unused Pin Settings 5.1.1.3. Dual-Purpose Pins Settings 5.1.1.4. Voltage Settings 5.1.1.5. Error Detection CRC Settings
5.5. Using Additional Intel® Quartus® Prime Software Tools x
5.5.1. Pin Planner 5.5.2. SSN Analyzer
1. Simultaneous Switching Noise (SSN) Analysis and Optimizations
2. Signal Integrity Analysis with Third-Party Tools
3. Mentor Graphics* PCB Design Tools Support
4. Cadence PCB Design Tools Support
5. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software
A. Intel® Quartus® Prime Standard Edition User Guides

1.7.1. Optimizing Pin Placements for Signal Integrity

The SSN Optimization logic option tells the Fitter to adjust the pin placement to reduce the SSN in the design.

The SSN Optimization logic option has three possible values: Off, Normal compilation, and Extra Effort.

If you use the SSN Optimization logic option, avoid creating location assignments for your pins. Instead, let the Fitter place the pins during compilation to meet the timing performance of your design.

To display the Fitter-placed pins use the Show Fitter Placements feature in the Pin Planner. To accept these suggested pin locations, you must back-annotate your pin assignments.

Note: Setting the SSN Optimization option to Extra effort may impact your design fMAX.
Figure 8. SSN Analysis Results Before and After Using the SSN Optimization Logic OptionThe image shows the pin placement before and after turning on the SSN Optimization logic option.
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