AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

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ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

1.1.1.3. Main Link RX

The FPGA Transceiver PHY RX includes on-chip 100 ohm differential termination and bias voltage generation.

You may add an RX repeater such as a retimer or a redriver in between the FPGA and the external DisplayPort connector to clean up jitter and compensate for losses. AC-coupling is optional for Main Link RX.

Table 7.  FPGA Transceiver PHY RX Operation Guidelines
FPGA Transceiver PHY Operations Description
Transceiver RX On-Chip Termination

By default, the Intel® Quartus® Prime software enables differential 100 ohm OCT and bias voltage generation. Your design does not require external 50 ohm termination and bias voltage (Vbias_RX).

RX Repeater (Redriver or Retimer)

To clean up jitter and compensate for signal losses, a sink device uses a redriver or retimer between the external DisplayPort connector and the FPGA RX. In such systems, the device places the repeater close to the external DisplayPort connector and regenerates the received DisplayPort signals.

  • The retimer includes the clock and data recovery (CDR) circuit that cleans up the jitter.
  • The redriver does not have a CDR circuit.

Refer to Table 8 for more information.

Table 8.  Guidelines on the Usage of the RX Repeater Device
Device Family VESA DisplayPort Standard version 1.2a Rates (RBR, HBR, HBR2) VESA DisplayPort Standard version 1.4 Rate (HBR3) Example Repeater
Intel® Stratix® 10 L-tile and H-tile Not Required 3 Not Required 3 –
Intel® Arria® 10 and Intel® Cyclone® 10 GX Not Required 3 Required 4
  • Parade Technologies PS8460 (Retimer)
  • Megachip MCD6000C1
Arria V Required 4 Not Applicable 5 TI SN75DP130 (Redriver)
Cyclone V Required 4 Not Applicable 5 TI SN75DP130 (Redriver)
Stratix V Not Required Not Applicable 5 –
3 Intel recommends that you perform signal integrity analysis to determine whether a retimer or redriver should be added between the DisplayPort RX connector and the FPGA for data rates up to HBR3; to compensate the insertion loss due to long cables or multiple cables with different signal qualities and weakness in the transmitter.
4 Configure the PMA settings of the repeater or retimer, so that the link quality between the repeater or retimer and FPGA is optimum.
5 This device does not support HBR3 data rate.
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