AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

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ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

1.1.1.1. Main Link TX

The Main Link TX drives doubly-terminated AC-coupled differential pairs.

The FPGA Transceiver PHY TX includes on-chip 100 ohm differential termination and bias voltage generation. You may add a repeater such as a retimer or a redriver in between the FPGA and the external DisplayPort connector to compensate for loss.

Table 1.  FPGA Transceiver PHY TX Operation Guidelines
FPGA Transceiver PHY Operations Description
Transceiver PHY TX Reference Clock Connection

A free-running 135 MHz differential clock (e.g. LVDS) is AC-coupled to a dedicated reference clock input of the transceiver bank. The reference clock input supports on-chip termination (OCT).

Enable OCT using a QSF assignment:

  • Intel® Stratix® 10 L-tile and H-tile devices

    set_instance_assignment -name XCVR_S10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to <dedicated refclk pin name>

  • Intel® Arria® 10 devices

    set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to <dedicated refclk pin name>

  • Intel® Cyclone® 10 GX devices

    set_instance_assignment -name XCVR_C10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to <dedicated refclk pin name>

  • Arria V, Cyclone V, and Stratix V devices

    set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to <dedicated refclk pin name>

Note: Your design does not require external termination if OCT is enabled.
Transceiver TX On-Chip Termination

By default, the Intel® Quartus® Prime software enables differential 100 ohm OCT and bias voltage generation. Your design does not require external 50 ohm termination and bias voltage (Vbias_TX).

Transceiver TX Channel Bonding

Bonding TX channels reduces on-chip channel-to-channel skew, which allows more skew margin at the board or system level to meet the DisplayPort Intel® FPGA IP Source inter-lane skew requirement.

Refer to Table 2 for more information.

Transceiver TX Voltage Swing and Pre-emphasis

DisplayPort TX specification for the Main Link allows four differential peak-to-peak voltage swing levels, and four pre-emphasis (Post Cursor1) levels. Certain combinations of voltage swing levels and pre-emphasis levels that result in differential peak-to-peak swing outside the allowable range (1.38 V) are not allowed.

The reconfiguration management module available in the Intel® Quartus® Prime design example includes a sub-module that translates the DisplayPort voltage swing and pre-emphasis levels to the FPGA transceiver setting. Refer to Table 3 for more information.

Use the reconfiguration management file and a sub-module of the Intel® Quartus® Prime design examples that maps the DisplayPort levels to the transceiver analog parameter setting.

  • Intel® Stratix® 10 L-tile and H-tile devices

    Reconfiguration management module : bitec_reconfig_alt_s10.v

    Sub-module: tx_analog mappings, rx_analog mappings

  • Intel® Arria® 10 devices

    Reconfiguration management module : bitec_reconfig_alt_a10.v

    Sub-module: tx_analog mappings, rx_analog mappings

  • Intel® Cyclone® 10 GX devices

    Reconfiguration management module : bitec_reconfig_alt_c10.v

    Sub-module: tx_analog mappings, rx_analog mappings

  • Arria V devices

    Reconfiguration management module : bitec_reconfig_alt_av.v

    Sub-module: dp_analog_mappings

  • Cyclone V devices

    Reconfiguration management module : reconfig_mgmt_hw_ctrl.v

    Sub-module: dp_analog_mappings

  • Stratix V devices

    Reconfiguration management module : bitec_reconfig_alt_sv.v

    Sub-module: dp_analog_mappings
TX Repeater (Redriver or Retimer)

To mitigate system signal losses, you may place a redriver or retimer between the FPGA and the external DisplayPort connector for a box-to-box connection. In such designs, place the repeater close to the external DisplayPort connector and generate the DisplayPort signals at the voltage and pre-emphasis levels determined during link training, instead of the FPGA.

In this case, you can turn off the Support analog reconfiguration option in the DisplayPort Intel® FPGA IP parameter editor and set the FPGA voltage swing in the QSF assignments. The selection of the appropriate signaling level between the FPGA and the repeater depend on the PCB loss and the equalization of the redriver/retimer input. The typical setting for the transmitter is 400 mV voltage swing without pre-emphasis.

Refer to Table 4 for more information.

Bonded TX channels placed in a single transceiver bank results in lower channel-to-channel skew, allowing more skew budget at the board level. For information about the maximum channel-to-channel skew, refer to the Device Datasheet.

You have the option to select bonding mode through the Transceiver PHY parameter editor.

Table 2.  Bonding Mode Selection Guidelines
Device Family Transceiver PHY Bonding Mode Notes
Intel® Stratix® 10 L-tile and H-tile/ Intel® Arria® 10/ Intel® Cyclone® 10 GX PMA and PCS bonding
  • Requires bonded TX channels to be placed contiguously
  • Logical channel 0 is selected as a bonding master
  • Uses x6/xN clock network driven by Master Clock Generation Block (MCGB). MCGB is enabled in the TX PLL (e.g. fPLL) parameter editor.
Note: The digital reset signal (tx_digitalreset) to all TX channels within a bonded group must meet a maximum skew tolerance of one-half the TX parallel clock cycle (tx_clkout). Refer to the Timing Constraints for Bonded PCS and PMA Channels section of the respective Transceiver PHY User Guides for more information.
Arria V xN –
Stratix V x6/xN –
Table 3.  Recommended Combinations of Voltage Swing and Pre-Emphasis LevelsThis table lists the 4 levels of voltage swing level defined in the Video Electronics Standards Association (VESA) DisplayPort Standard. The combination of these levels is independent of the devices. Intel FPGA devices support all 4 levels. The mapping between the DisplayPort levels and the actual PMA values is provided in the DisplayPort Intel® FPGA IP design examples.
Voltage Swing Level Pre-Emphasis Level
0 1 2 3
0 Supported Supported Supported Supported
1 Supported Supported Supported Not allowed
2 Supported Supported Not allowed Not allowed
3 Supported Not allowed Not allowed Not allowed
Table 4.  Guidelines on the Usage of the TX Repeater Device
Device Family DisplayPort version 1.2 Rates (RBR, HBR, HBR2) DisplayPort version 1.4 Rate (HBR3) Example Repeater
Intel® Stratix® 10 L-tile and H-tile Not Required Not Required –
Intel® Arria® 10 Not Required Not Required –
Intel® Cyclone® 10 GX Not Required Not Required –
Arria V Required 1 Not Applicable 2 TI SN75DP130 (Redriver)
Cyclone V Required 1 Not Applicable 2 TI SN75DP130 (Redriver)
Stratix V Not Required Not Applicable 2 –
1 Configure the PMA settings of the repeater, so that the link quality between the repeater and FPGA is optimum.
2 This device does not support HBR3 data rate.
Level Two Title