Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683628
Date 12/28/2017
Public
Document Table of Contents

1.3.1. Simulation Environment

Altera performs the following tests on the Low Latency 40-100GbE MAC and PHY IP core in the simulation environment using internal and third party standard bus functional models (BFM):

  • Constrained random tests that cover randomized frame size and contents
  • Randomized error injection tests that inject Frame Check Sequence (FCS) field errors, runt packets, and corrupt control characters, and then check for the proper response from the IP core
  • Assertion based tests to confirm proper behavior of the IP core with respect to the specification
  • Extensive coverage of our runtime configuration space and proper behavior in all possible modes of operation