AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

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ID 683671
Date 6/12/2018
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Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices x
Features Hardware and Software Requirements Functional Description Simulation Hardware Testing Interface Signals Configuration Registers and Status Registers Document Revision History for AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Functional Description x
Design Components Clocking and Reset Scheme
Simulation x
Procedure Testbench Test Case
Hardware Testing x
Hardware Setup Test Procedure
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Test Procedure

  1. Download the reference design from Design Store and restore the design using Intel® Quartus® Prime software.
  2. Launch the Intel® Quartus® Prime software and open the project file (top.qpf).
  3. Before running the design compilation, go to Assignments > Settings. Under IP Settings category, select Always regenerate design files for IP cores and Generate IP simulation model when generating IP.
  4. Click Processing > Start Compilation to compile the design.
    Note: You may experience timing violations after running compilation for the design. To resolve these timing violations, you must launch the Design Space Explorer II in the Intel® Quartus® Prime software (Tools > Design Space Explorer II) and perform seed sweep to get the best quality of fit.
  5. After the design is compiled successfully, a programming file (top.sof) is generated and located in <project_directory/output_files>.
  6. Set up the Intel® Stratix® 10 GX H-Tile Signal Integrity (SI) Development Board.
    1. Connect the programming cable to the JTAG connection port (CN1).
    2. Connect the board to the power supply input (J103).
    3. Connect the 10G SFP+ transceiver module along with optical loopback cable to SFP+ port (J29).
  7. In the Intel® Quartus® Prime software, select Tools > Programmer to launch the programmer.
  8. Configure the Intel® Stratix® 10 GX H-Tile SI development board using the generated programming file (altera_eth_top.sof).
  9. Reset the Ethernet design by using the push button (USER_PB0).
    Note: The design must be reset whenever you begin a new test.
  10. In the Intel® Quartus® Prime software, click Tools > System Debugging Tools and launch the system console.
  11. In the System Console command shell, change the directory to project_directory/hwtesting/system_console.

You can now run the predefined hardware tests using the provided test commands listed in Table 4.

Table 4.  Test Command
Test Case Test Command Description
SFP+ external loopback source gen_conf.tcl The generator generates and sends about 100 000 packets with random bytes (maximum packet length = 1518 bytes). Wait 1 minutes for it to complete its tasks.
source monitor_conf.tcl The monitor checks the number of good and bad packets received.
source show_stats.tcl This script displays the values of the statistics counters
Avalon® -ST reverse loopback source loopback_conf.tcl This command enables the Avalon® -ST loopback. This test is used with an external tester such as Spirent tester

The following diagrams show excerpts of the output, which shows that the Ethernet packet generator configuration, the Ethernet packet monitor status, and the TX and RX statistics counters.

Figure 10. Sample Test Output—Ethernet Packet Generator Configuration
Figure 11. Sample Test Output—Ethernet Packet Monitor Status
Figure 12. Sample Test Output—TX Statistics Counter
Figure 13. Sample Test Output—RX Statistics Counter
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