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1. Logic Array Blocks and Adaptive Logic Modules in Intel® Cyclone® 10 GX Devices
2. Embedded Memory Blocks in Intel® Cyclone® 10 GX Devices
3. Variable Precision DSP Blocks in Intel® Cyclone® 10 GX Devices
4. Clock Networks and PLLs in Intel® Cyclone® 10 GX Devices
5. I/O and High Speed I/O in Intel® Cyclone® 10 GX Devices
6. External Memory Interfaces in Intel® Cyclone® 10 GX Devices
7. Configuration, Design Security, and Remote System Upgrades in Intel® Cyclone® 10 GX Devices
8. SEU Mitigation for Intel® Cyclone® 10 GX Devices
9. JTAG Boundary-Scan Testing in Intel® Cyclone® 10 GX Devices
10. Power Management in Intel® Cyclone® 10 GX Devices
2.1. Types of Embedded Memory
2.2. Embedded Memory Design Guidelines for Intel® Cyclone® 10 GX Devices
2.3. Embedded Memory Features
2.4. Embedded Memory Modes
2.5. Embedded Memory Clocking Modes
2.6. Parity Bit in Embedded Memory Blocks
2.7. Byte Enable in Embedded Memory Blocks
2.8. Memory Blocks Packed Mode Support
2.9. Memory Blocks Address Clock Enable Support
2.10. Memory Blocks Asynchronous Clear
2.11. Memory Blocks Error Correction Code Support
2.12. Embedded Memory Blocks in Intel® Cyclone® 10 GX Devices Revision History
3.4.1. Input Register Bank
3.4.2. Pipeline Register
3.4.3. Pre-Adder for Fixed-Point Arithmetic
3.4.4. Internal Coefficient for Fixed-Point Arithmetic
3.4.5. Multipliers
3.4.6. Adder
3.4.7. Accumulator and Chainout Adder for Fixed-Point Arithmetic
3.4.8. Systolic Registers for Fixed-Point Arithmetic
3.4.9. Double Accumulation Register for Fixed-Point Arithmetic
3.4.10. Output Register Bank
4.2.1. PLL Usage
4.2.2. PLL Architecture
4.2.3. PLL Control Signals
4.2.4. Clock Feedback Modes
4.2.5. Clock Multiplication and Division
4.2.6. Programmable Phase Shift
4.2.7. Programmable Duty Cycle
4.2.8. PLL Cascading
4.2.9. Reference Clock Sources
4.2.10. Clock Switchover
4.2.11. PLL Reconfiguration and Dynamic Phase Shift
5.1. I/O and Differential I/O Buffers in Intel® Cyclone® 10 GX Devices
5.2. I/O Standards and Voltage Levels in Intel® Cyclone® 10 GX Devices
5.3. Intel FPGA I/O IP Cores for Intel® Cyclone® 10 GX Devices
5.4. I/O Resources in Intel® Cyclone® 10 GX Devices
5.5. Architecture and General Features of I/Os in Intel® Cyclone® 10 GX Devices
5.6. High Speed Source-Synchronous SERDES and DPA in Intel® Cyclone® 10 GX Devices
5.7. Using the I/Os and High Speed I/Os in Intel® Cyclone® 10 GX Devices
5.8. I/O and High Speed I/O in Intel® Cyclone® 10 GX Devices Revision History
5.5.1. I/O Element Structure in Intel® Cyclone® 10 GX Devices
5.5.2. Features of I/O Pins in Intel® Cyclone® 10 GX Devices
5.5.3. Programmable IOE Features in Intel® Cyclone® 10 GX Devices
5.5.4. On-Chip I/O Termination in Intel® Cyclone® 10 GX Devices
5.5.5. External I/O Termination for Intel® Cyclone® 10 GX Devices
5.5.4.1. RS OCT without Calibration in Intel® Cyclone® 10 GX Devices
5.5.4.2. RS OCT with Calibration in Intel® Cyclone® 10 GX Devices
5.5.4.3. RT OCT with Calibration in Intel® Cyclone® 10 GX Devices
5.5.4.4. Dynamic OCT
5.5.4.5. Differential Input RD OCT
5.5.4.6. OCT Calibration Block in Intel® Cyclone® 10 GX Devices
5.6.1. Intel® Cyclone® 10 GX LVDS SERDES Usage Modes
5.6.2. SERDES Circuitry
5.6.3. SERDES I/O Standards Support in Intel® Cyclone® 10 GX Devices
5.6.4. Differential Transmitter in Intel® Cyclone® 10 GX Devices
5.6.5. Differential Receiver in Intel® Cyclone® 10 GX Devices
5.6.6. PLLs and Clocking for Intel® Cyclone® 10 GX Devices
5.6.7. Timing and Optimization for Intel® Cyclone® 10 GX Devices
5.6.6.1. Clocking Differential Transmitters
5.6.6.2. Clocking Differential Receivers
5.6.6.3. Guideline: LVDS Reference Clock Source
5.6.6.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
5.6.6.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
5.6.6.6. Guideline: Pin Placement for Differential Channels
5.6.6.7. LVDS Interface with External PLL Mode
5.7.1. I/O and High-Speed I/O General Guidelines for Intel® Cyclone® 10 GX Devices
5.7.2. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
5.7.3. Guideline: Maximum Current Driving I/O Pins While Turned Off and During Power Sequencing
5.7.4. Guideline: Maximum DC Current Restrictions
5.7.5. Guideline: LVDS SERDES IP Core Instantiation
5.7.6. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
5.7.7. Guideline: Minimizing High Jitter Impact on Intel® Cyclone® 10 GX GPIO Performance
5.7.8. Guideline: Usage of I/O Bank 2A for External Memory Interfaces
6.1. Key Features of the Intel® Cyclone® 10 GX External Memory Interface Solution
6.2. Memory Standards Supported by Intel® Cyclone® 10 GX Devices
6.3. External Memory Interface Widths in Intel® Cyclone® 10 GX Devices
6.4. External Memory Interface I/O Pins in Intel® Cyclone® 10 GX Devices
6.5. Memory Interfaces Support in Intel® Cyclone® 10 GX Device Packages
6.6. External Memory Interface IP Support in Intel® Cyclone® 10 GX Devices
6.7. External Memory Interface Architecture of Intel® Cyclone® 10 GX Devices
6.8. External Memory Interfaces in Intel® Cyclone® 10 GX Devices Revision History
7.1. Enhanced Configuration and Configuration via Protocol
7.2. Configuration Schemes
7.3. Configuration Details
7.4. Remote System Upgrades Using Active Serial Scheme
7.5. Design Security
7.6. Configuration, Design Security, and Remote System Upgrades in Intel® Cyclone® 10 GX Devices Revision History
9.1. BST Operation Control
9.2. I/O Voltage for JTAG Operation
9.3. Performing BST
9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
9.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
9.6. IEEE Std. 1149.1 Boundary-Scan Register
9.7. IEEE Std. 1149.6 Boundary-Scan Register
9.8. JTAG Boundary-Scan Testing in Intel® Cyclone® 10 GX Devices Revision History
10.1. Power Consumption
10.2. Programmable Power Technology
10.3. Power Sense Line
10.4. Voltage Sensor
10.5. Temperature Sensing Diode
10.6. Power-On Reset Circuitry
10.7. Power Sequencing Considerations for Intel® Cyclone® 10 GX Devices
10.8. Power Supply Design
10.9. Power Management in Intel® Cyclone® 10 GX Devices Revision History
WYSIWYG Atom to Access the Voltage Sensor Block
10.4.2.1.1. Configuration Registers for the Core Access Mode
10.4.2.1.2. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11
10.4.2.1.3. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
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10.4.2.1. Accessing the Voltage Sensor Using FPGA Core Access
During user mode, you can implement a soft IP to access the voltage sensor block. To access the voltage sensor block from the core fabric, you need to include the following WYSIWYG atom in your Intel® Quartus® Prime project:
WYSIWYG Atom to Access the Voltage Sensor Block
twentynm_vsblock<name>(
.clk (<input>, clock signal from core),
.reset(<input>, reset signal from core),
.corectl(<input>, core enable signal from core),
.coreconfig(<input>, config signal from core),
.confin(<input>, config data signal from core),
.chsel(<input>, 4 bits channel selection signal from core),
.eoc(<output>, end of conversion signal from vsblock),
.eos(<output>, end of sequence signal from vsblock),
.dataout(<output>, 12 bits data out of vsblock));
Port Name | Type | Description |
---|---|---|
clk | Input | Clock signal from the core. The voltage sensor supports up to 11-MHz clock. |
reset | Input | Active high reset signal. The reset signal has to asynchronously transition from high-to-low for the voltage sensor to start conversion. All registers are cleared and the internal voltage sensor clock is gated off when the reset signal is high. |
corectl | Input | Active high signal. "1" indicates the voltage sensor is enabled for core access. "0" indicates the voltage sensor is disabled for core access. |
coreconfig | Input | Serial configuration signal. Active high. |
confin | Input | Serial input data from the core to configure the configuration register. The configuration register for the core access mode is 8-bit wide. LSB is the first bit shifted in. |
chsel[3:0] | Input | 4-bit channel address. Specifying the channel to be converted. |
eoc | Output | Indicates the end of the conversion. This signal is asserted after the conversion of each channel data. |
eos | Output | Indicates the end of sequence. This signal is asserted after the completion of the conversion in one cycle of the selected sequence. |
dataout[11:0] | Output |
|