AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
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Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Connect cpu_subsystem Components

Connect the component signals below by clicking the dots across from the appropriate signals, or by right-clicking the signal and choosing from the drop-down menu.

Follow these steps to connect the components:

Figure 11. Illustrated Clock and Reset Component Connections for cpu_subsystem
Table 3.  Component Connections for cpu_subsystem
Source Component/Signal Target Component/Signal
mem_clk/out_clk pipeline_bridge/clk
cpu_clk/out_clk
  • cpu_reset/clk
  • cpu/clk
  • onchip_ram/clk1
  • jtag_uart/clk
mem_reset/out_reset
  • cpu/reset
  • onchip_ram/reset1
  • jtag_uart/reset
  • pipleline_bridge/reset
cpu_reset/out_reset
  • cpu/reset
  • onchip_ram/reset1
  • jtag_uart/reset
  • pipleline_bridge/reset
cpu/data_master
  • onchip_ram/s1
  • jtag_uart/avalon_jtag_slave
  • pipleline_bridge/s0
cpu/instruction_master onchip_ram/s1

Compare the finished connections to the following figure:

Figure 12. Component Connections for cpu_subsystem

System Connectivity Error appears in the System Messages tab. To access this tab, click View > System Messages. The System Connectivity Error occurs because when the base address of the Avalon-MM slaves are not assigned, which can cause address overlap.

Follow these steps to assign the Base address to the value shown in the following figure. Click the “lock” icon to lock the address.

  1. In the Base column, click the value for Avalon Memory Mapped Slave (Description column) of the cpu component and type 12000.
  2. Find the Avalon Memory Mapped Slave entry for the onchip_ram component and type 10000 as the value in the Base column.
  3. Find the Avalon Memory Mapped Slave entry for the jtag_uart component and type 12800 as the value in the Base column.
    Figure 13. Base Address Assignments for cpu_subsystem Components
  4. To resolve any remaining system connectivity errors, in the System Messages tab, click Sync All System Info in the bottom of the GUI. This synchronizes the component instantiations with their .ip files.
  5. To resolve errors in the parameterization of the cpu component (the name of the component is still red), double-click cpu and you can see the Parameterization Messages in the Parameters tab. Platform Designer separates the messages for system connectivity and component parameterization, which simplifies the error and resolution compared to the combined messaging in Platform Designer (Standard).
    Figure 14. Parameterization Messages
  6. In the Vectors tab, set Reset vector memory and Exception vector memory both to onchip_ram.s1 to resolve the error messages.
  7. Click File > Save to save the project. There is no need to generate the RTL for the Platform Designer system at this time. Click Move up one level of hierarchy to return to top_level.qsys system.
    Figure 15. Move Up One Hierarchy Level
Level Two Title