AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
Public
Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Synchronize IP Results

When you synchronize IP files, Platform Designer checks IP file references.
  1. In the Intel® Quartus® Prime Pro Edition, click Files in the Project Navigator and browse to memory_tester_subsystem.v.
  2. Delete the empty entity RTL memory_tester_subsystem.v since we now have the actual memory_tester_subsystem implementation.

    The files included in memory_tester_subsystem are not complete though. We are missing IP components in the pattern generator system and pattern checker system.

  3. Open the pattern_generator_system.qsys and pattern_checker_system.qsys in Platform Designer and save them without generating HDL. This designates the IP components in these systems for elaboration during compilation.

    Each time you open a Platform Designer project, Platform Designer automatically checks the IP file references and opens a dialog box if there is any mismatch. In the following figure, IP Synchronization detects the Platform Designer system includes these IP, but the Intel® Quartus® Prime Pro Edition project does not. This dialog box informs you when you must add these files to the project..

    Figure 42. IP Synchronization Dialog Box
  4. Click OK and the Intel® Quartus® Prime Pro Edition synchronizes the file references.
  5. Examine the Project Navigator and these new files appear:
    Figure 43. Files Added through IP Synchronization
  6. Click Processing > Start Compilation to compile the project. The Intel® Quartus® Prime Pro Edition software may return missing file errors, for example: 
    "Instance ‘ abc|def|ghi ’ instantiates undefined entity ‘ xyz ’ "
    This type of error is caused when an expected IP file is missing. Resolve it by adding the xyz.ip file to the project.
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