Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

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ID 683864
Date 6/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.3.7. Fiber Weave

  • A composite of fiber and resin make up the PCB material. The strand bundles of fiber run perpendicular to each other. Depending on the orientation of the weave relative to the trace, there can be a resin or a fiber bundle beneath the trace. The differing dielectric constants of these two materials may introduce a phase skew among signals that comprise a differential pair, manifesting itself as an AC common mode noise at the receiver, affecting both the voltage and timing margin at the receiver. This is the fiber weave effect. To mitigate the fiber weave effect, specify a dense spread of weave (1078, 1035, 3313, 1067, etc.) rather than a sparse weave (106, 1080) for prepreg1 and core.
  • Use a 2-ply (1078x2, 1078+1067, 1035x2, etc.) prepreg and core to mitigate the fiber weave effect. Especially for the 112G PAM4 application, it is better to use 2-ply (1035x2, 1078x2, 1035+1078) prepreg and core.
  • For more details about the fiber weave effect, refer to AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing.
Related Information
1 "Prepreg" is an abbreviation of "pre-impregnated material," in this case, referring to the PCB fiberglass impregnated with resin (an epoxy-based material) used in multilayer boards.
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